Son T. Dinh

Array ( [id] => 616410 [patent_doc_number] => 07144822 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-05 [patent_title] => 'High density plasma process for optimum film quality and electrical results' [patent_app_type] => utility [patent_app_number] => 10/072357 [patent_app_country] => US [patent_app_date] => 2002-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2703 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/144/07144822.pdf [firstpage_image] =>[orig_patent_app_number] => 10072357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1177418 [patent_doc_number] => 06743711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Method for forming dual damascene line structure' [patent_app_type] => B2 [patent_app_number] => 10/062716 [patent_app_country] => US [patent_app_date] => 2002-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 3302 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/743/06743711.pdf [firstpage_image] =>[orig_patent_app_number] => 10062716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6755938 [patent_doc_number] => 20030003715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Method for forming dual damascene line structure' [patent_app_type] => new [patent_app_number] => 10/062717 [patent_app_country] => US [patent_app_date] => 2002-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3177 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003715.pdf [firstpage_image] =>[orig_patent_app_number] => 10062717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6692745 [patent_doc_number] => 20030040177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Method for forming metal interconnections using electroless plating' [patent_app_type] => new [patent_app_number] => 10/066227 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3117 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20030040177.pdf [firstpage_image] =>[orig_patent_app_number] => 10066227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6696952 [patent_doc_number] => 20030109146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Oxynitride device and method using non-stoichiometric silicon oxide' [patent_app_type] => new [patent_app_number] => 10/061637 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3870 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20030109146.pdf [firstpage_image] =>[orig_patent_app_number] => 10061637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1165564 [patent_doc_number] => 06756304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Method for producing via-connections in a substrate and substrate equipped with same' [patent_app_type] => B1 [patent_app_number] => 10/030157 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 3475 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756304.pdf [firstpage_image] =>[orig_patent_app_number] => 10030157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 662709 [patent_doc_number] => 07101770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Capacitive techniques to reduce noise in high speed interconnections' [patent_app_type] => utility [patent_app_number] => 10/060801 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 9153 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/101/07101770.pdf [firstpage_image] =>[orig_patent_app_number] => 10060801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6563506 [patent_doc_number] => 20020164876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Method for finishing polysilicon or amorphous substrate structures' [patent_app_type] => new [patent_app_number] => 10/054697 [patent_app_country] => US [patent_app_date] => 2002-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3167 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20020164876.pdf [firstpage_image] =>[orig_patent_app_number] => 10054697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6659670 [patent_doc_number] => 20030134461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'METHOD FOR REDUCING OXIDATION ENCROACHMENT OF STACKED GATE LAYER' [patent_app_type] => new [patent_app_number] => 10/043147 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2899 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20030134461.pdf [firstpage_image] =>[orig_patent_app_number] => 10043147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5968551 [patent_doc_number] => 20020090811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Method of fabricating metal lines in a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/035257 [patent_app_country] => US [patent_app_date] => 2002-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2470 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20020090811.pdf [firstpage_image] =>[orig_patent_app_number] => 10035257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1270257 [patent_doc_number] => 06653214 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Measured via-hole etching' [patent_app_type] => B1 [patent_app_number] => 10/034747 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 33 [patent_no_of_words] => 6540 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653214.pdf [firstpage_image] =>[orig_patent_app_number] => 10034747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6306868 [patent_doc_number] => 20020094687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Method of fabricating semiconductor device for preventing contaminating particle generation' [patent_app_type] => new [patent_app_number] => 10/029147 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3328 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20020094687.pdf [firstpage_image] =>[orig_patent_app_number] => 10029147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6847168 [patent_doc_number] => 20030166335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Method of forming wiring in semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/032687 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2029 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20030166335.pdf [firstpage_image] =>[orig_patent_app_number] => 10032687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 720011 [patent_doc_number] => 07049237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Methods for planarization of Group VIII metal-containing surfaces using oxidizing gases' [patent_app_type] => utility [patent_app_number] => 10/032357 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5241 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049237.pdf [firstpage_image] =>[orig_patent_app_number] => 10032357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1193005 [patent_doc_number] => 06730588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method of forming SiGe gate electrode' [patent_app_type] => B1 [patent_app_number] => 10/026407 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2681 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730588.pdf [firstpage_image] =>[orig_patent_app_number] => 10026407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1375996 [patent_doc_number] => 06559030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method of forming a recessed polysilicon filled trench' [patent_app_type] => B1 [patent_app_number] => 10/015987 [patent_app_country] => US [patent_app_date] => 2001-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2800 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559030.pdf [firstpage_image] =>[orig_patent_app_number] => 10015987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1080497 [patent_doc_number] => 06835655 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-28 [patent_title] => 'Method of implanting copper barrier material to improve electrical performance' [patent_app_type] => B1 [patent_app_number] => 09/994397 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/835/06835655.pdf [firstpage_image] =>[orig_patent_app_number] => 09994397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7385292 [patent_doc_number] => 20040020973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Bump formation method and bump forming apparatus to semiconductor wafer' [patent_app_type] => new [patent_app_number] => 10/415587 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12619 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20040020973.pdf [firstpage_image] =>[orig_patent_app_number] => 10415587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6570998 [patent_doc_number] => 20020084467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Nitride semiconductor device with reduced polarization fields' [patent_app_type] => new [patent_app_number] => 09/992192 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4161 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20020084467.pdf [firstpage_image] =>[orig_patent_app_number] => 09992192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6765022 [patent_doc_number] => 20030099420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Electro-optic modulator' [patent_app_type] => new [patent_app_number] => 09/991337 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2102 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20030099420.pdf [firstpage_image] =>[orig_patent_app_number] => 09991337 [rel_patent_id] =>[rel_patent_doc_number] =>)