Search

Sonya C. Harris

Examiner (ID: 5172)

Most Active Art Unit
3309
Art Unit(s)
3309, 3736, 3739, 3311
Total Applications
399
Issued Applications
311
Pending Applications
46
Abandoned Applications
42

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20063353 [patent_doc_number] => 20250201575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SELECTIVE DEPOSITION FOR MITIGATING CORNER LOSS IN SEMICONDUCTOR FABRICATION [patent_app_type] => utility [patent_app_number] => 18/984294 [patent_app_country] => US [patent_app_date] => 2024-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18984294 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/984294
SELECTIVE DEPOSITION FOR MITIGATING CORNER LOSS IN SEMICONDUCTOR FABRICATION Dec 16, 2024 Pending
Array ( [id] => 20267010 [patent_doc_number] => 12438008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Method of producing assembly of stacked elements having resin layer with fillers [patent_app_type] => utility [patent_app_number] => 18/743313 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743313
Method of producing assembly of stacked elements having resin layer with fillers Jun 13, 2024 Issued
Array ( [id] => 20404400 [patent_doc_number] => 12494380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Amplifier modules with power transistor die and peripheral ground connections [patent_app_type] => utility [patent_app_number] => 18/637489 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6545 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637489 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637489
Amplifier modules with power transistor die and peripheral ground connections Apr 16, 2024 Issued
Array ( [id] => 19206290 [patent_doc_number] => 20240178189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => APPARATUSES INCLUDING REDISTRIBUTION LAYERS AND EMBEDDED INTERCONNECT STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/435822 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435822 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435822
APPARATUSES INCLUDING REDISTRIBUTION LAYERS AND EMBEDDED INTERCONNECT STRUCTURES Feb 6, 2024 Pending
Array ( [id] => 19206290 [patent_doc_number] => 20240178189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => APPARATUSES INCLUDING REDISTRIBUTION LAYERS AND EMBEDDED INTERCONNECT STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/435822 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435822 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435822
APPARATUSES INCLUDING REDISTRIBUTION LAYERS AND EMBEDDED INTERCONNECT STRUCTURES Feb 6, 2024 Pending
Array ( [id] => 20002401 [patent_doc_number] => 20250140623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => HIGH-TEMPERATURE WIDE BANDGAP POWER MODULE AND PREPARATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/397980 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 621 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397980
HIGH-TEMPERATURE WIDE BANDGAP POWER MODULE AND PREPARATION METHOD THEREOF Dec 26, 2023 Pending
Array ( [id] => 20002401 [patent_doc_number] => 20250140623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => HIGH-TEMPERATURE WIDE BANDGAP POWER MODULE AND PREPARATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/397980 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 621 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397980
HIGH-TEMPERATURE WIDE BANDGAP POWER MODULE AND PREPARATION METHOD THEREOF Dec 26, 2023 Pending
Array ( [id] => 20002401 [patent_doc_number] => 20250140623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => HIGH-TEMPERATURE WIDE BANDGAP POWER MODULE AND PREPARATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/397980 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 621 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397980
HIGH-TEMPERATURE WIDE BANDGAP POWER MODULE AND PREPARATION METHOD THEREOF Dec 26, 2023 Pending
Array ( [id] => 18927082 [patent_doc_number] => 20240030086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => BGA STIM PACKAGE ARCHITECTURE FOR HIGH PERFORMANCE SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/376341 [patent_app_country] => US [patent_app_date] => 2023-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18376341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/376341
BGA STIM PACKAGE ARCHITECTURE FOR HIGH PERFORMANCE SYSTEMS Oct 2, 2023 Pending
Array ( [id] => 18898765 [patent_doc_number] => 20240014250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => Semiconductor Devices Including Resistor Structures [patent_app_type] => utility [patent_app_number] => 18/371328 [patent_app_country] => US [patent_app_date] => 2023-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18371328 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/371328
Semiconductor devices including resistor structures Sep 20, 2023 Issued
Array ( [id] => 18898600 [patent_doc_number] => 20240014085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => CHIP PROTECTIVE FILM AND METHOD FOR MANUFACTURING SAME, AND CHIP [patent_app_type] => utility [patent_app_number] => 18/459006 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459006 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/459006
Chip protective film and method for manufacturing same, and chip Aug 29, 2023 Issued
Array ( [id] => 20111459 [patent_doc_number] => 12362195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Leadframe with a metal oxide coating and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/451022 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451022 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451022
Leadframe with a metal oxide coating and method of forming the same Aug 15, 2023 Issued
Array ( [id] => 18821161 [patent_doc_number] => 20230395502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS [patent_app_type] => utility [patent_app_number] => 18/362044 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362044 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362044
Metallization lines on integrated circuit products Jul 30, 2023 Issued
Array ( [id] => 19749444 [patent_doc_number] => 20250038009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => STRESS RELIEF SAWN QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/361747 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361747 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361747
STRESS RELIEF SAWN QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE Jul 27, 2023 Pending
Array ( [id] => 19749444 [patent_doc_number] => 20250038009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => STRESS RELIEF SAWN QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/361747 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361747 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361747
STRESS RELIEF SAWN QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE Jul 27, 2023 Pending
Array ( [id] => 19749444 [patent_doc_number] => 20250038009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => STRESS RELIEF SAWN QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/361747 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361747 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361747
STRESS RELIEF SAWN QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE Jul 27, 2023 Pending
Array ( [id] => 18927170 [patent_doc_number] => 20240030174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => QUAD FLAT NO-LEAD (QFN) PACKAGE WITH BACKSIDE CONDUCTIVE MATERIAL AND DIRECT CONTACT INTERCONNECT BUILD-UP STRUCTURE AND METHOD FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/224964 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/224964
QUAD FLAT NO-LEAD (QFN) PACKAGE WITH BACKSIDE CONDUCTIVE MATERIAL AND DIRECT CONTACT INTERCONNECT BUILD-UP STRUCTURE AND METHOD FOR MAKING THE SAME Jul 20, 2023 Pending
Array ( [id] => 18439910 [patent_doc_number] => 20230187205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SUBSTRATE PACKAGE WITH GLASS DIELECTRIC [patent_app_type] => utility [patent_app_number] => 18/165422 [patent_app_country] => US [patent_app_date] => 2023-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18165422 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/165422
SUBSTRATE PACKAGE WITH GLASS DIELECTRIC Feb 6, 2023 Abandoned
Array ( [id] => 18456279 [patent_doc_number] => 20230197561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => POWER SEMICONDUCTOR MODULE COMPRISING A SUBSTRATE, POWER SEMICONDUCTOR COMPONENTS AND COMPRISING A PRESSURE BODY [patent_app_type] => utility [patent_app_number] => 18/078854 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18078854 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/078854
POWER SEMICONDUCTOR MODULE COMPRISING A SUBSTRATE, POWER SEMICONDUCTOR COMPONENTS AND COMPRISING A PRESSURE BODY Dec 8, 2022 Pending
Array ( [id] => 18456279 [patent_doc_number] => 20230197561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => POWER SEMICONDUCTOR MODULE COMPRISING A SUBSTRATE, POWER SEMICONDUCTOR COMPONENTS AND COMPRISING A PRESSURE BODY [patent_app_type] => utility [patent_app_number] => 18/078854 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18078854 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/078854
POWER SEMICONDUCTOR MODULE COMPRISING A SUBSTRATE, POWER SEMICONDUCTOR COMPONENTS AND COMPRISING A PRESSURE BODY Dec 8, 2022 Pending
Menu