
Sonya C. Harris
Examiner (ID: 12542)
| Most Active Art Unit | 3309 |
| Art Unit(s) | 3739, 3309, 3311, 3736 |
| Total Applications | 399 |
| Issued Applications | 311 |
| Pending Applications | 46 |
| Abandoned Applications | 42 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20118394
[patent_doc_number] => 12368112
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => Electronic component and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/901784
[patent_app_country] => US
[patent_app_date] => 2022-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901784
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/901784 | Electronic component and manufacturing method thereof | Aug 31, 2022 | Issued |
Array
(
[id] => 19007821
[patent_doc_number] => 20240071892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => MOLDED PACKAGE WITH PRESS-FIT CONDUCTIVE PINS
[patent_app_type] => utility
[patent_app_number] => 17/900446
[patent_app_country] => US
[patent_app_date] => 2022-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7168
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17900446
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/900446 | MOLDED PACKAGE WITH PRESS-FIT CONDUCTIVE PINS | Aug 30, 2022 | Pending |
Array
(
[id] => 20496941
[patent_doc_number] => 12538835
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-27
[patent_title] => Integrated chip package including a crack-resistant lid structure and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 17/898834
[patent_app_country] => US
[patent_app_date] => 2022-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 39
[patent_no_of_words] => 8809
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898834
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/898834 | Integrated chip package including a crack-resistant lid structure and methods of forming the same | Aug 29, 2022 | Issued |
Array
(
[id] => 19007876
[patent_doc_number] => 20240071947
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 17/823157
[patent_app_country] => US
[patent_app_date] => 2022-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16018
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823157
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/823157 | SEMICONDUCTOR PACKAGE AND METHOD | Aug 29, 2022 | Issued |
Array
(
[id] => 19524014
[patent_doc_number] => 12125754
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-22
[patent_title] => Sensor package substrate, sensor module including the same, and electronic component embedded substrate
[patent_app_type] => utility
[patent_app_number] => 17/894584
[patent_app_country] => US
[patent_app_date] => 2022-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 35
[patent_no_of_words] => 6624
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894584
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/894584 | Sensor package substrate, sensor module including the same, and electronic component embedded substrate | Aug 23, 2022 | Issued |
Array
(
[id] => 18827664
[patent_doc_number] => 11842954
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-12
[patent_title] => Method of manufacturing semiconductor devices and corresponding semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/887838
[patent_app_country] => US
[patent_app_date] => 2022-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 17
[patent_no_of_words] => 3164
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887838
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/887838 | Method of manufacturing semiconductor devices and corresponding semiconductor device | Aug 14, 2022 | Issued |
Array
(
[id] => 19277301
[patent_doc_number] => 12027433
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-02
[patent_title] => Semiconductor package and method for making the same
[patent_app_type] => utility
[patent_app_number] => 17/885401
[patent_app_country] => US
[patent_app_date] => 2022-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 24
[patent_no_of_words] => 7405
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885401
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/885401 | Semiconductor package and method for making the same | Aug 9, 2022 | Issued |
Array
(
[id] => 18663260
[patent_doc_number] => 20230309286
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 17/882725
[patent_app_country] => US
[patent_app_date] => 2022-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8452
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882725
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/882725 | Memory device and manufacturing method therefor | Aug 7, 2022 | Issued |
Array
(
[id] => 18593368
[patent_doc_number] => 11742280
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-29
[patent_title] => Integrated circuits with backside power rails
[patent_app_type] => utility
[patent_app_number] => 17/860253
[patent_app_country] => US
[patent_app_date] => 2022-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 68
[patent_no_of_words] => 12512
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860253
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/860253 | Integrated circuits with backside power rails | Jul 7, 2022 | Issued |
Array
(
[id] => 18882967
[patent_doc_number] => 20240006336
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-04
[patent_title] => SHIELD TO REDUCE SUBSTRATE ELECTROMAGNETIC INTERFERENCE AND WARPAGE
[patent_app_type] => utility
[patent_app_number] => 17/852816
[patent_app_country] => US
[patent_app_date] => 2022-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7739
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852816
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/852816 | SHIELD TO REDUCE SUBSTRATE ELECTROMAGNETIC INTERFERENCE AND WARPAGE | Jun 28, 2022 | Pending |
Array
(
[id] => 18112950
[patent_doc_number] => 20230005830
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => SEMICONDUCTOR APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/809086
[patent_app_country] => US
[patent_app_date] => 2022-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4795
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 377
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809086
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/809086 | Semiconductor apparatus | Jun 26, 2022 | Issued |
Array
(
[id] => 17917552
[patent_doc_number] => 20220319948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => DOUBLE-SIDED COOLABLE SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/844455
[patent_app_country] => US
[patent_app_date] => 2022-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7993
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844455
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/844455 | Double-sided coolable semiconductor package | Jun 19, 2022 | Issued |
Array
(
[id] => 20276553
[patent_doc_number] => 12446342
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Imaging element and imaging apparatus
[patent_app_type] => utility
[patent_app_number] => 17/842570
[patent_app_country] => US
[patent_app_date] => 2022-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 2343
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842570
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/842570 | Imaging element and imaging apparatus | Jun 15, 2022 | Issued |
Array
(
[id] => 18669955
[patent_doc_number] => 11776867
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-03
[patent_title] => Chip package
[patent_app_type] => utility
[patent_app_number] => 17/839500
[patent_app_country] => US
[patent_app_date] => 2022-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 7686
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17839500
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/839500 | Chip package | Jun 13, 2022 | Issued |
Array
(
[id] => 20360215
[patent_doc_number] => 12476221
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-18
[patent_title] => Fabrication method of stacked device and stacked device
[patent_app_type] => utility
[patent_app_number] => 17/838295
[patent_app_country] => US
[patent_app_date] => 2022-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 2105
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838295
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/838295 | Fabrication method of stacked device and stacked device | Jun 12, 2022 | Issued |
Array
(
[id] => 17886494
[patent_doc_number] => 20220301972
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => PACKAGE WITH THERMAL INTERFACE MATERIAL RETAINING STRUCTURES ON DIE AND HEAT SPREADER
[patent_app_type] => utility
[patent_app_number] => 17/834753
[patent_app_country] => US
[patent_app_date] => 2022-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21160
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834753
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/834753 | Package with thermal interface material retaining structures on die and heat spreader | Jun 6, 2022 | Issued |
Array
(
[id] => 17886569
[patent_doc_number] => 20220302047
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => ADVANCED SEAL RING STRUCTURE AND METHOD OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/833120
[patent_app_country] => US
[patent_app_date] => 2022-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8240
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833120
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/833120 | Advanced seal ring structure and method of making the same | Jun 5, 2022 | Issued |
Array
(
[id] => 19830024
[patent_doc_number] => 12250831
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-11
[patent_title] => Semiconductor device and method of manufacturing the same, and electronic apparatus including semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/805575
[patent_app_country] => US
[patent_app_date] => 2022-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 26
[patent_no_of_words] => 9267
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805575
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/805575 | Semiconductor device and method of manufacturing the same, and electronic apparatus including semiconductor device | Jun 5, 2022 | Issued |
Array
(
[id] => 17855128
[patent_doc_number] => 20220285171
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-08
[patent_title] => Integrated Circuit Package Pad and Methods of Forming
[patent_app_type] => utility
[patent_app_number] => 17/664458
[patent_app_country] => US
[patent_app_date] => 2022-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8398
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664458
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/664458 | Integrated circuit package pad and methods of forming | May 22, 2022 | Issued |
Array
(
[id] => 18144491
[patent_doc_number] => 20230018343
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => Package Assembly Including Lid With Additional Stress Mitigating Feet And Methods Of Making The Same
[patent_app_type] => utility
[patent_app_number] => 17/748335
[patent_app_country] => US
[patent_app_date] => 2022-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19826
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748335
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/748335 | Package assembly including lid with additional stress mitigating feet and methods of making the same | May 18, 2022 | Issued |