Search

Sonya N. Wright

Examiner (ID: 6088, Phone: (571)272-5857 , Office: P/1672 )

Most Active Art Unit
1629
Art Unit(s)
1629, 1796, 1613, 1621, 1672, 1614, 1762, 1626
Total Applications
765
Issued Applications
560
Pending Applications
32
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6921576 [patent_doc_number] => 20010029061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Insulator/metal bonding island for active-area silver epoxy bonding' [patent_app_type] => new [patent_app_number] => 09/818192 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2578 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20010029061.pdf [firstpage_image] =>[orig_patent_app_number] => 09818192 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/818192
Insulator/metal bonding island for active-area silver epoxy bonding Mar 25, 2001 Abandoned
Array ( [id] => 6895225 [patent_doc_number] => 20010026015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Semiconductor device having reliable electrical connection' [patent_app_type] => new [patent_app_number] => 09/816061 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026015.pdf [firstpage_image] =>[orig_patent_app_number] => 09816061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/816061
Semiconductor device having reliable electrical connection Mar 25, 2001 Abandoned
Array ( [id] => 1574689 [patent_doc_number] => 06468871 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Method of forming bipolar transistor salicided emitter using selective laser annealing' [patent_app_type] => B1 [patent_app_number] => 09/816824 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1857 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/468/06468871.pdf [firstpage_image] =>[orig_patent_app_number] => 09816824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/816824
Method of forming bipolar transistor salicided emitter using selective laser annealing Mar 22, 2001 Issued
Array ( [id] => 1528016 [patent_doc_number] => 06479327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/812592 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 70 [patent_no_of_words] => 17424 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 429 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479327.pdf [firstpage_image] =>[orig_patent_app_number] => 09812592 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812592
Semiconductor device and method for manufacturing the same Mar 20, 2001 Issued
09/787661 Method for producing an amorphous or polycrystalline layer on an insulaitng region Mar 20, 2001 Abandoned
Array ( [id] => 7093174 [patent_doc_number] => 20010034101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'Method for producing semiconductor device' [patent_app_type] => new [patent_app_number] => 09/811552 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4195 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034101.pdf [firstpage_image] =>[orig_patent_app_number] => 09811552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811552
Method for producing semiconductor device Mar 19, 2001 Issued
Array ( [id] => 1419225 [patent_doc_number] => 06506659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-14 [patent_title] => 'High performance bipolar transistor' [patent_app_type] => B2 [patent_app_number] => 09/811321 [patent_app_country] => US [patent_app_date] => 2001-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5384 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506659.pdf [firstpage_image] =>[orig_patent_app_number] => 09811321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811321
High performance bipolar transistor Mar 16, 2001 Issued
Array ( [id] => 1205593 [patent_doc_number] => 06716722 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Method of producing a bonded wafer and the bonded wafer' [patent_app_type] => B1 [patent_app_number] => 09/787038 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7910 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716722.pdf [firstpage_image] =>[orig_patent_app_number] => 09787038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/787038
Method of producing a bonded wafer and the bonded wafer Mar 12, 2001 Issued
Array ( [id] => 1469741 [patent_doc_number] => 06406942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-18 [patent_title] => 'Flip chip type semiconductor device and method for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/801901 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 41 [patent_no_of_words] => 8709 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/406/06406942.pdf [firstpage_image] =>[orig_patent_app_number] => 09801901 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/801901
Flip chip type semiconductor device and method for manufacturing the same Mar 8, 2001 Issued
Array ( [id] => 6434931 [patent_doc_number] => 20020127828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Method of processing wafer' [patent_app_type] => new [patent_app_number] => 09/786511 [patent_app_country] => US [patent_app_date] => 2001-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20020127828.pdf [firstpage_image] =>[orig_patent_app_number] => 09786511 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/786511
Method of processing wafer Mar 5, 2001 Abandoned
Array ( [id] => 1474349 [patent_doc_number] => 06387719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method for improving adhesion' [patent_app_type] => B1 [patent_app_number] => 09/795731 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2406 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387719.pdf [firstpage_image] =>[orig_patent_app_number] => 09795731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795731
Method for improving adhesion Feb 27, 2001 Issued
Array ( [id] => 7636669 [patent_doc_number] => 06379986 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method of forming tunnel oxide film for superconducting X-ray sensor element' [patent_app_type] => B1 [patent_app_number] => 09/778462 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1286 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/379/06379986.pdf [firstpage_image] =>[orig_patent_app_number] => 09778462 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778462
Method of forming tunnel oxide film for superconducting X-ray sensor element Feb 6, 2001 Issued
Array ( [id] => 7105373 [patent_doc_number] => 20010004545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-21 [patent_title] => 'Epitaxial cleaning process using hcl and N-type dopant gas to reduce defect density and auto doping effects' [patent_app_type] => new-utility [patent_app_number] => 09/771428 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5573 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20010004545.pdf [firstpage_image] =>[orig_patent_app_number] => 09771428 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771428
Epitaxial cleaning process using HCL and N-type dopant gas to reduce defect density and auto doping effects Jan 25, 2001 Issued
Array ( [id] => 1453459 [patent_doc_number] => 06461904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Structure and method for making a notched transistor with spacers' [patent_app_type] => B1 [patent_app_number] => 09/757451 [patent_app_country] => US [patent_app_date] => 2001-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1977 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/461/06461904.pdf [firstpage_image] =>[orig_patent_app_number] => 09757451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/757451
Structure and method for making a notched transistor with spacers Jan 8, 2001 Issued
Array ( [id] => 1366271 [patent_doc_number] => 06566146 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method for double-sided patterning of high temperature superconducting circuits' [patent_app_type] => B1 [patent_app_number] => 09/743082 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 2903 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566146.pdf [firstpage_image] =>[orig_patent_app_number] => 09743082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/743082
Method for double-sided patterning of high temperature superconducting circuits Jan 3, 2001 Issued
Array ( [id] => 6892081 [patent_doc_number] => 20010018243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Method for fabricating a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/751941 [patent_app_country] => US [patent_app_date] => 2001-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2918 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20010018243.pdf [firstpage_image] =>[orig_patent_app_number] => 09751941 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751941
Method for fabricating a semiconductor device Jan 1, 2001 Issued
Array ( [id] => 1536031 [patent_doc_number] => 06337236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-01-08 [patent_title] => 'Semiconductor device and method for forming the same' [patent_app_type] => B2 [patent_app_number] => 09/750064 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 6190 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337236.pdf [firstpage_image] =>[orig_patent_app_number] => 09750064 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750064
Semiconductor device and method for forming the same Dec 28, 2000 Issued
Array ( [id] => 6629569 [patent_doc_number] => 20020086452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Methods of forming semiconductor structure' [patent_app_type] => new [patent_app_number] => 09/749692 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5143 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20020086452.pdf [firstpage_image] =>[orig_patent_app_number] => 09749692 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749692
Methods of forming semiconductor structure Dec 27, 2000 Issued
Array ( [id] => 7040499 [patent_doc_number] => 20010005311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'Heat sink for chip stacking applications' [patent_app_type] => new-utility [patent_app_number] => 09/741822 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2290 [patent_no_of_claims] => 104 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005311.pdf [firstpage_image] =>[orig_patent_app_number] => 09741822 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741822
Heat sink for chip stacking applications Dec 21, 2000 Issued
Array ( [id] => 1507357 [patent_doc_number] => 06440811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method of fabricating a poly-poly capacitor with a SiGe BiCMOS integration scheme' [patent_app_type] => B1 [patent_app_number] => 09/745361 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 3070 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440811.pdf [firstpage_image] =>[orig_patent_app_number] => 09745361 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745361
Method of fabricating a poly-poly capacitor with a SiGe BiCMOS integration scheme Dec 20, 2000 Issued
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