
Sonya N. Wright
Examiner (ID: 6088, Phone: (571)272-5857 , Office: P/1672 )
| Most Active Art Unit | 1629 |
| Art Unit(s) | 1629, 1796, 1613, 1621, 1672, 1614, 1762, 1626 |
| Total Applications | 765 |
| Issued Applications | 560 |
| Pending Applications | 32 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1458842
[patent_doc_number] => 06426279
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-30
[patent_title] => 'Epitaxial delta doping for retrograde channel profile'
[patent_app_type] => B1
[patent_app_number] => 09/598911
[patent_app_country] => US
[patent_app_date] => 2000-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 2603
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/426/06426279.pdf
[firstpage_image] =>[orig_patent_app_number] => 09598911
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/598911 | Epitaxial delta doping for retrograde channel profile | Jun 21, 2000 | Issued |
Array
(
[id] => 1549755
[patent_doc_number] => 06346465
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-12
[patent_title] => 'Semiconductor device with silicide contact structure and fabrication method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/598502
[patent_app_country] => US
[patent_app_date] => 2000-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 20
[patent_no_of_words] => 6002
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/346/06346465.pdf
[firstpage_image] =>[orig_patent_app_number] => 09598502
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/598502 | Semiconductor device with silicide contact structure and fabrication method thereof | Jun 21, 2000 | Issued |
Array
(
[id] => 1532380
[patent_doc_number] => 06410369
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Soi-body selective link method and apparatus'
[patent_app_type] => B1
[patent_app_number] => 09/591511
[patent_app_country] => US
[patent_app_date] => 2000-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 23
[patent_no_of_words] => 4487
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/410/06410369.pdf
[firstpage_image] =>[orig_patent_app_number] => 09591511
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/591511 | Soi-body selective link method and apparatus | Jun 11, 2000 | Issued |
Array
(
[id] => 1459669
[patent_doc_number] => 06391804
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-21
[patent_title] => 'Method and apparatus for uniform direct radiant heating in a rapid thermal processing reactor'
[patent_app_type] => B1
[patent_app_number] => 09/590824
[patent_app_country] => US
[patent_app_date] => 2000-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3760
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/391/06391804.pdf
[firstpage_image] =>[orig_patent_app_number] => 09590824
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/590824 | Method and apparatus for uniform direct radiant heating in a rapid thermal processing reactor | Jun 8, 2000 | Issued |
Array
(
[id] => 4270572
[patent_doc_number] => 06323054
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'Lateral P-I-N photodiode element with high quantum efficiency for a CMOS image sensor'
[patent_app_type] => 1
[patent_app_number] => 9/583398
[patent_app_country] => US
[patent_app_date] => 2000-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1804
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/323/06323054.pdf
[firstpage_image] =>[orig_patent_app_number] => 583398
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/583398 | Lateral P-I-N photodiode element with high quantum efficiency for a CMOS image sensor | May 30, 2000 | Issued |
Array
(
[id] => 1312402
[patent_doc_number] => 06610607
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-26
[patent_title] => 'Method to define and tailor process limited lithographic features using a modified hard mask process'
[patent_app_type] => B1
[patent_app_number] => 09/578362
[patent_app_country] => US
[patent_app_date] => 2000-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 2536
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/610/06610607.pdf
[firstpage_image] =>[orig_patent_app_number] => 09578362
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/578362 | Method to define and tailor process limited lithographic features using a modified hard mask process | May 24, 2000 | Issued |
Array
(
[id] => 1440959
[patent_doc_number] => 06335224
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-01
[patent_title] => 'Protection of microelectronic devices during packaging'
[patent_app_type] => B1
[patent_app_number] => 09/572562
[patent_app_country] => US
[patent_app_date] => 2000-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 5126
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 22
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/335/06335224.pdf
[firstpage_image] =>[orig_patent_app_number] => 09572562
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/572562 | Protection of microelectronic devices during packaging | May 15, 2000 | Issued |
Array
(
[id] => 4327045
[patent_doc_number] => 06319799
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'High mobility heterojunction transistor and method'
[patent_app_type] => 1
[patent_app_number] => 9/568091
[patent_app_country] => US
[patent_app_date] => 2000-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1711
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/319/06319799.pdf
[firstpage_image] =>[orig_patent_app_number] => 568091
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/568091 | High mobility heterojunction transistor and method | May 8, 2000 | Issued |
Array
(
[id] => 1517256
[patent_doc_number] => 06500721
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-31
[patent_title] => 'Bipolar thin-film transistors and method for forming'
[patent_app_type] => B1
[patent_app_number] => 09/564342
[patent_app_country] => US
[patent_app_date] => 2000-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3325
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/500/06500721.pdf
[firstpage_image] =>[orig_patent_app_number] => 09564342
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/564342 | Bipolar thin-film transistors and method for forming | May 2, 2000 | Issued |
Array
(
[id] => 5986226
[patent_doc_number] => 20020098621
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-25
[patent_title] => 'Method of mounting a passive component over an integrated circuit package substrate'
[patent_app_type] => new
[patent_app_number] => 09/560031
[patent_app_country] => US
[patent_app_date] => 2000-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2710
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20020098621.pdf
[firstpage_image] =>[orig_patent_app_number] => 09560031
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/560031 | Method of mounting a passive component over an integrated circuit package substrate | Apr 26, 2000 | Issued |
Array
(
[id] => 1411938
[patent_doc_number] => 06524904
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-25
[patent_title] => 'Method of fabricating semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/551542
[patent_app_country] => US
[patent_app_date] => 2000-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 20
[patent_no_of_words] => 5085
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/524/06524904.pdf
[firstpage_image] =>[orig_patent_app_number] => 09551542
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/551542 | Method of fabricating semiconductor device | Apr 17, 2000 | Issued |
Array
(
[id] => 5986278
[patent_doc_number] => 20020098636
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-25
[patent_title] => 'Cmos process'
[patent_app_type] => new
[patent_app_number] => 09/549948
[patent_app_country] => US
[patent_app_date] => 2000-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1856
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20020098636.pdf
[firstpage_image] =>[orig_patent_app_number] => 09549948
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/549948 | Cmos process | Apr 13, 2000 | Abandoned |
Array
(
[id] => 1393905
[patent_doc_number] => 06520348
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-18
[patent_title] => 'Multiple inclined wafer holder for improved vapor transport and reflux for sealed ampoule diffusion process'
[patent_app_type] => B1
[patent_app_number] => 09/542622
[patent_app_country] => US
[patent_app_date] => 2000-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3134
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/520/06520348.pdf
[firstpage_image] =>[orig_patent_app_number] => 09542622
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/542622 | Multiple inclined wafer holder for improved vapor transport and reflux for sealed ampoule diffusion process | Apr 3, 2000 | Issued |
Array
(
[id] => 1261557
[patent_doc_number] => 06664196
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-16
[patent_title] => 'Method of cleaning electronic device and method of fabricating the same'
[patent_app_type] => B1
[patent_app_number] => 09/526174
[patent_app_country] => US
[patent_app_date] => 2000-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 8394
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/664/06664196.pdf
[firstpage_image] =>[orig_patent_app_number] => 09526174
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/526174 | Method of cleaning electronic device and method of fabricating the same | Mar 14, 2000 | Issued |
Array
(
[id] => 6630330
[patent_doc_number] => 20020086488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-04
[patent_title] => 'Method of manufacturing a semiconductor device comprising a bipolar transistor and a capacitor'
[patent_app_type] => new
[patent_app_number] => 09/520061
[patent_app_country] => US
[patent_app_date] => 2000-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4905
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0086/20020086488.pdf
[firstpage_image] =>[orig_patent_app_number] => 09520061
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/520061 | Method of manufacturing a semiconductor device comprising a bipolar transistor and a capacitor | Mar 6, 2000 | Issued |
Array
(
[id] => 5874059
[patent_doc_number] => 20020048884
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-04-25
[patent_title] => 'Vertical source/drain contact semiconductor'
[patent_app_type] => new
[patent_app_number] => 09/510102
[patent_app_country] => US
[patent_app_date] => 2000-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2510
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20020048884.pdf
[firstpage_image] =>[orig_patent_app_number] => 09510102
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/510102 | Vertical source/drain contact semiconductor | Feb 21, 2000 | Abandoned |
Array
(
[id] => 4407302
[patent_doc_number] => 06238991
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-29
[patent_title] => 'Fabrication process of semiconductor device having an epitaxial substrate'
[patent_app_type] => 1
[patent_app_number] => 9/489942
[patent_app_country] => US
[patent_app_date] => 2000-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 20
[patent_no_of_words] => 6939
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/238/06238991.pdf
[firstpage_image] =>[orig_patent_app_number] => 489942
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/489942 | Fabrication process of semiconductor device having an epitaxial substrate | Jan 23, 2000 | Issued |
Array
(
[id] => 1352362
[patent_doc_number] => 06583493
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-24
[patent_title] => 'Single event upset hardening technique for bipolar devices'
[patent_app_type] => B1
[patent_app_number] => 09/488193
[patent_app_country] => US
[patent_app_date] => 2000-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1836
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/583/06583493.pdf
[firstpage_image] =>[orig_patent_app_number] => 09488193
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/488193 | Single event upset hardening technique for bipolar devices | Jan 19, 2000 | Issued |
Array
(
[id] => 7640339
[patent_doc_number] => 06395575
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-28
[patent_title] => 'Method of manufacturing sensor and resistor element'
[patent_app_type] => B1
[patent_app_number] => 09/463144
[patent_app_country] => US
[patent_app_date] => 2000-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4294
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 4
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/395/06395575.pdf
[firstpage_image] =>[orig_patent_app_number] => 09463144
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/463144 | Method of manufacturing sensor and resistor element | Jan 19, 2000 | Issued |
Array
(
[id] => 7644002
[patent_doc_number] => 06429036
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Backside illumination of CMOS image sensor'
[patent_app_type] => B1
[patent_app_number] => 09/483362
[patent_app_country] => US
[patent_app_date] => 2000-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 1771
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 9
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/429/06429036.pdf
[firstpage_image] =>[orig_patent_app_number] => 09483362
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/483362 | Backside illumination of CMOS image sensor | Jan 13, 2000 | Issued |