
Sonya N. Wright
Examiner (ID: 6088, Phone: (571)272-5857 , Office: P/1672 )
| Most Active Art Unit | 1629 |
| Art Unit(s) | 1629, 1796, 1613, 1621, 1672, 1614, 1762, 1626 |
| Total Applications | 765 |
| Issued Applications | 560 |
| Pending Applications | 32 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6870156
[patent_doc_number] => 20030082845
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-01
[patent_title] => ' PACKAGE FOR MULTIPLE INTEGRATED CIRCUITS AND METHOD OF MAKING\n '
[patent_app_type] => voluntary
[patent_app_number] => 09/483212
[patent_app_country] => US
[patent_app_date] => 2000-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5313
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20030082845.pdf
[firstpage_image] =>[orig_patent_app_number] => 09483212
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/483212 | PACKAGE FOR MULTIPLE INTEGRATED CIRCUITS AND METHOD OF MAKINGn | Jan 13, 2000 | Abandoned |
Array
(
[id] => 4408069
[patent_doc_number] => 06265254
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-24
[patent_title] => 'Semiconductor integrated circuit devices and a method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/475048
[patent_app_country] => US
[patent_app_date] => 1999-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 79
[patent_figures_cnt] => 79
[patent_no_of_words] => 28814
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/265/06265254.pdf
[firstpage_image] =>[orig_patent_app_number] => 475048
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/475048 | Semiconductor integrated circuit devices and a method of manufacturing the same | Dec 29, 1999 | Issued |
Array
(
[id] => 4378641
[patent_doc_number] => 06303508
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Superior silicon carbide integrated circuits and method of fabricating'
[patent_app_type] => 1
[patent_app_number] => 9/464861
[patent_app_country] => US
[patent_app_date] => 1999-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3486
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/303/06303508.pdf
[firstpage_image] =>[orig_patent_app_number] => 464861
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/464861 | Superior silicon carbide integrated circuits and method of fabricating | Dec 15, 1999 | Issued |
Array
(
[id] => 4289398
[patent_doc_number] => 06235569
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-22
[patent_title] => 'Circuit and method for low voltage, voltage sense amplifier'
[patent_app_type] => 1
[patent_app_number] => 9/451982
[patent_app_country] => US
[patent_app_date] => 1999-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5167
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/235/06235569.pdf
[firstpage_image] =>[orig_patent_app_number] => 451982
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/451982 | Circuit and method for low voltage, voltage sense amplifier | Nov 29, 1999 | Issued |
Array
(
[id] => 1414381
[patent_doc_number] => 06521504
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-18
[patent_title] => 'Semiconductor device and method of fabricating the same'
[patent_app_type] => B1
[patent_app_number] => 09/448761
[patent_app_country] => US
[patent_app_date] => 1999-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 6001
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/521/06521504.pdf
[firstpage_image] =>[orig_patent_app_number] => 09448761
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/448761 | Semiconductor device and method of fabricating the same | Nov 23, 1999 | Issued |
Array
(
[id] => 1386219
[patent_doc_number] => 06548383
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-15
[patent_title] => 'Twin well methods of forming CMOS integrated circuitry'
[patent_app_type] => B1
[patent_app_number] => 09/441912
[patent_app_country] => US
[patent_app_date] => 1999-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 2812
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/548/06548383.pdf
[firstpage_image] =>[orig_patent_app_number] => 09441912
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/441912 | Twin well methods of forming CMOS integrated circuitry | Nov 16, 1999 | Issued |
Array
(
[id] => 1458681
[patent_doc_number] => 06426241
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-30
[patent_title] => 'Method for forming three-dimensional circuitization and circuits formed'
[patent_app_type] => B1
[patent_app_number] => 09/439112
[patent_app_country] => US
[patent_app_date] => 1999-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 18
[patent_no_of_words] => 7162
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/426/06426241.pdf
[firstpage_image] =>[orig_patent_app_number] => 09439112
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/439112 | Method for forming three-dimensional circuitization and circuits formed | Nov 11, 1999 | Issued |
Array
(
[id] => 1415570
[patent_doc_number] => 06511901
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-28
[patent_title] => 'Metal redistribution layer having solderable pads and wire bondable pads'
[patent_app_type] => B1
[patent_app_number] => 09/434711
[patent_app_country] => US
[patent_app_date] => 1999-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 2231
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/511/06511901.pdf
[firstpage_image] =>[orig_patent_app_number] => 09434711
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/434711 | Metal redistribution layer having solderable pads and wire bondable pads | Nov 4, 1999 | Issued |
Array
(
[id] => 4368899
[patent_doc_number] => 06287930
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-11
[patent_title] => 'Methods of forming bipolar junction transistors having trench-based base electrodes'
[patent_app_type] => 1
[patent_app_number] => 9/425812
[patent_app_country] => US
[patent_app_date] => 1999-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 4174
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/287/06287930.pdf
[firstpage_image] =>[orig_patent_app_number] => 425812
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/425812 | Methods of forming bipolar junction transistors having trench-based base electrodes | Oct 24, 1999 | Issued |
Array
(
[id] => 4353283
[patent_doc_number] => 06218214
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-17
[patent_title] => 'Integrated circuit package for flip chip and method of forming same'
[patent_app_type] => 1
[patent_app_number] => 9/422011
[patent_app_country] => US
[patent_app_date] => 1999-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2557
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/218/06218214.pdf
[firstpage_image] =>[orig_patent_app_number] => 422011
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/422011 | Integrated circuit package for flip chip and method of forming same | Oct 20, 1999 | Issued |
Array
(
[id] => 1514419
[patent_doc_number] => 06420196
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-16
[patent_title] => 'Method of forming an inkjet printhead using part of active circuitry layers to form sacrificial structures'
[patent_app_type] => B1
[patent_app_number] => 09/425194
[patent_app_country] => US
[patent_app_date] => 1999-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 76
[patent_figures_cnt] => 103
[patent_no_of_words] => 9310
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/420/06420196.pdf
[firstpage_image] =>[orig_patent_app_number] => 09425194
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/425194 | Method of forming an inkjet printhead using part of active circuitry layers to form sacrificial structures | Oct 18, 1999 | Issued |
Array
(
[id] => 4408891
[patent_doc_number] => 06228733
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-08
[patent_title] => 'Non-selective epitaxial depostion technology'
[patent_app_type] => 1
[patent_app_number] => 9/400632
[patent_app_country] => US
[patent_app_date] => 1999-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 1673
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/228/06228733.pdf
[firstpage_image] =>[orig_patent_app_number] => 400632
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/400632 | Non-selective epitaxial depostion technology | Sep 22, 1999 | Issued |
Array
(
[id] => 4353876
[patent_doc_number] => 06218254
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-17
[patent_title] => 'Method of fabricating a self-aligned bipolar junction transistor in silicon carbide and resulting devices'
[patent_app_type] => 1
[patent_app_number] => 9/401602
[patent_app_country] => US
[patent_app_date] => 1999-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 5356
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/218/06218254.pdf
[firstpage_image] =>[orig_patent_app_number] => 401602
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/401602 | Method of fabricating a self-aligned bipolar junction transistor in silicon carbide and resulting devices | Sep 21, 1999 | Issued |
Array
(
[id] => 1324546
[patent_doc_number] => 06602803
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-05
[patent_title] => 'Direct attachment semiconductor chip to organic substrate'
[patent_app_type] => B2
[patent_app_number] => 09/401572
[patent_app_country] => US
[patent_app_date] => 1999-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 4780
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/602/06602803.pdf
[firstpage_image] =>[orig_patent_app_number] => 09401572
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/401572 | Direct attachment semiconductor chip to organic substrate | Sep 21, 1999 | Issued |
Array
(
[id] => 1553503
[patent_doc_number] => 06348382
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-19
[patent_title] => 'Integration process to increase high voltage breakdown performance'
[patent_app_type] => B1
[patent_app_number] => 09/392391
[patent_app_country] => US
[patent_app_date] => 1999-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 10
[patent_no_of_words] => 4915
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/348/06348382.pdf
[firstpage_image] =>[orig_patent_app_number] => 09392391
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/392391 | Integration process to increase high voltage breakdown performance | Sep 8, 1999 | Issued |
Array
(
[id] => 4312472
[patent_doc_number] => 06242313
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Use of polysilicon field plates to improve high voltage bipolar device breakdown voltage'
[patent_app_type] => 1
[patent_app_number] => 9/389891
[patent_app_country] => US
[patent_app_date] => 1999-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2559
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/242/06242313.pdf
[firstpage_image] =>[orig_patent_app_number] => 389891
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/389891 | Use of polysilicon field plates to improve high voltage bipolar device breakdown voltage | Sep 2, 1999 | Issued |
Array
(
[id] => 4408513
[patent_doc_number] => 06265293
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-24
[patent_title] => 'CMOS transistors fabricated in optimized RTA scheme'
[patent_app_type] => 1
[patent_app_number] => 9/384121
[patent_app_country] => US
[patent_app_date] => 1999-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 3164
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/265/06265293.pdf
[firstpage_image] =>[orig_patent_app_number] => 384121
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/384121 | CMOS transistors fabricated in optimized RTA scheme | Aug 26, 1999 | Issued |
Array
(
[id] => 4327100
[patent_doc_number] => 06319803
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Method of fabricating semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/373001
[patent_app_country] => US
[patent_app_date] => 1999-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3810
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/319/06319803.pdf
[firstpage_image] =>[orig_patent_app_number] => 373001
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/373001 | Method of fabricating semiconductor device | Aug 11, 1999 | Issued |
Array
(
[id] => 4312670
[patent_doc_number] => 06242324
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Method for fabricating singe crystal materials over CMOS devices'
[patent_app_type] => 1
[patent_app_number] => 9/371782
[patent_app_country] => US
[patent_app_date] => 1999-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6905
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/242/06242324.pdf
[firstpage_image] =>[orig_patent_app_number] => 371782
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/371782 | Method for fabricating singe crystal materials over CMOS devices | Aug 9, 1999 | Issued |
Array
(
[id] => 4357843
[patent_doc_number] => 06255143
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => 'Flip chip thermally enhanced ball grid array'
[patent_app_type] => 1
[patent_app_number] => 9/366752
[patent_app_country] => US
[patent_app_date] => 1999-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2693
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 314
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/255/06255143.pdf
[firstpage_image] =>[orig_patent_app_number] => 366752
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/366752 | Flip chip thermally enhanced ball grid array | Aug 3, 1999 | Issued |