Sonya N. Wright

Array ( [id] => 4381544 [patent_doc_number] => 06261932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method of fabricating Schottky diode and related structure' [patent_app_type] => 1 [patent_app_number] => 9/364232 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 6179 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261932.pdf [firstpage_image] =>[orig_patent_app_number] => 364232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4190905 [patent_doc_number] => 06043117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and method of making' [patent_app_type] => 1 [patent_app_number] => 9/361692 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4305 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043117.pdf [firstpage_image] =>[orig_patent_app_number] => 361692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4258511 [patent_doc_number] => 06258643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method for forming twin gate CMOS' [patent_app_type] => 1 [patent_app_number] => 9/344691 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2378 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258643.pdf [firstpage_image] =>[orig_patent_app_number] => 344691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4259142 [patent_doc_number] => 06258686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Manufacturing method of semiconductor device and semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/333681 [patent_app_country] => US [patent_app_date] => 1999-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 4762 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258686.pdf [firstpage_image] =>[orig_patent_app_number] => 333681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4405853 [patent_doc_number] => 06171914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Synchronized implant process to simplify NLDD/PLDD stage and N+/P+stage into one implant' [patent_app_type] => 1 [patent_app_number] => 9/332432 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1919 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171914.pdf [firstpage_image] =>[orig_patent_app_number] => 332432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318849 [patent_doc_number] => 06248646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Discrete wafer array process' [patent_app_type] => 1 [patent_app_number] => 9/330572 [patent_app_country] => US [patent_app_date] => 1999-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1797 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248646.pdf [firstpage_image] =>[orig_patent_app_number] => 330572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4301450 [patent_doc_number] => 06251702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Use of an oxide surface to facilitate gate break on a carrier substrate for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/318221 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2600 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251702.pdf [firstpage_image] =>[orig_patent_app_number] => 318221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4404976 [patent_doc_number] => 06232146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Semiconductor device including combed bond pad opening, assemblies and methods' [patent_app_type] => 1 [patent_app_number] => 9/314873 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3695 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232146.pdf [firstpage_image] =>[orig_patent_app_number] => 314873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1415542 [patent_doc_number] => 06511899 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Controlled cleavage process using pressurized fluid' [patent_app_type] => B1 [patent_app_number] => 09/306692 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 9494 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/511/06511899.pdf [firstpage_image] =>[orig_patent_app_number] => 09306692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4404840 [patent_doc_number] => 06232135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Passivation of ink jet printheads' [patent_app_type] => 1 [patent_app_number] => 9/294732 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4386 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232135.pdf [firstpage_image] =>[orig_patent_app_number] => 294732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4214956 [patent_doc_number] => 06087201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method of manufacturing ball grid array electronic component' [patent_app_type] => 1 [patent_app_number] => 9/249071 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 77 [patent_no_of_words] => 16825 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087201.pdf [firstpage_image] =>[orig_patent_app_number] => 249071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4350405 [patent_doc_number] => 06291303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method for manufacturing a bipolar junction device' [patent_app_type] => 1 [patent_app_number] => 9/215643 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2443 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291303.pdf [firstpage_image] =>[orig_patent_app_number] => 215643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4354853 [patent_doc_number] => 06200879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Using epitaxially grown wells for reducing junction capacitances' [patent_app_type] => 1 [patent_app_number] => 9/210271 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3330 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200879.pdf [firstpage_image] =>[orig_patent_app_number] => 210271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6973575 [patent_doc_number] => 20010003660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-14 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => new-utility [patent_app_number] => 09/206561 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9017 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20010003660.pdf [firstpage_image] =>[orig_patent_app_number] => 09206561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4234794 [patent_doc_number] => 06165819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Semiconductor device, method of producing semiconductor device and semiconductor device mounting structure' [patent_app_type] => 1 [patent_app_number] => 9/206151 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 93 [patent_no_of_words] => 24558 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165819.pdf [firstpage_image] =>[orig_patent_app_number] => 206151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4169225 [patent_doc_number] => 06140196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method of fabricating high power bipolar junction transistor' [patent_app_type] => 1 [patent_app_number] => 9/203711 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1976 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140196.pdf [firstpage_image] =>[orig_patent_app_number] => 203711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459222 [patent_doc_number] => 06391676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Thermoelectric module and a method of fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/200972 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 48 [patent_no_of_words] => 6517 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391676.pdf [firstpage_image] =>[orig_patent_app_number] => 09200972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4125224 [patent_doc_number] => 06127250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method of increasing package reliability by designing in plane CTE gradients' [patent_app_type] => 1 [patent_app_number] => 9/196681 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 16380 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127250.pdf [firstpage_image] =>[orig_patent_app_number] => 196681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4232967 [patent_doc_number] => 06117738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method for fabricating a high-bias semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/196933 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117738.pdf [firstpage_image] =>[orig_patent_app_number] => 196933 [rel_patent_id] =>[rel_patent_doc_number] =>)