Search

Sophia T. Nguyen

Examiner (ID: 13973)

Most Active Art Unit
2822
Art Unit(s)
2893, 2822, 2821
Total Applications
655
Issued Applications
250
Pending Applications
133
Abandoned Applications
284

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15939745 [patent_doc_number] => 20200161506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => Method for Producing a Ceramic Converter Element, Ceramic Converter Element, and Optoelectronic Component [patent_app_type] => utility [patent_app_number] => 16/198108 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16198108 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/198108
Method for producing a ceramic converter element, ceramic converter element, and optoelectronic component Nov 20, 2018 Issued
Array ( [id] => 14350667 [patent_doc_number] => 20190157306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => ACTIVE DEVICE SUBSTRATE AND FABRICATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/197382 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197382 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197382
Active device substrate and fabricating method thereof Nov 20, 2018 Issued
Array ( [id] => 15939145 [patent_doc_number] => 20200161206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR MANUFACTURING PROCESS [patent_app_type] => utility [patent_app_number] => 16/197351 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197351 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197351
SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR MANUFACTURING PROCESS Nov 19, 2018 Abandoned
Array ( [id] => 14385513 [patent_doc_number] => 20190166669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => PRINTED CIRCUIT BOARD FOR INTEGRATED LED DRIVER [patent_app_type] => utility [patent_app_number] => 16/184565 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184565
Printed circuit board for integrated LED driver Nov 7, 2018 Issued
Array ( [id] => 14385513 [patent_doc_number] => 20190166669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => PRINTED CIRCUIT BOARD FOR INTEGRATED LED DRIVER [patent_app_type] => utility [patent_app_number] => 16/184565 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184565
Printed circuit board for integrated LED driver Nov 7, 2018 Issued
Array ( [id] => 14385513 [patent_doc_number] => 20190166669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => PRINTED CIRCUIT BOARD FOR INTEGRATED LED DRIVER [patent_app_type] => utility [patent_app_number] => 16/184565 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184565
Printed circuit board for integrated LED driver Nov 7, 2018 Issued
Array ( [id] => 14385513 [patent_doc_number] => 20190166669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => PRINTED CIRCUIT BOARD FOR INTEGRATED LED DRIVER [patent_app_type] => utility [patent_app_number] => 16/184565 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184565
Printed circuit board for integrated LED driver Nov 7, 2018 Issued
Array ( [id] => 14285193 [patent_doc_number] => 20190139881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => SECURITY DEVICE SUCH THAT A SMART CARD [patent_app_type] => utility [patent_app_number] => 16/181643 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181643 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181643
SECURITY DEVICE SUCH THAT A SMART CARD Nov 5, 2018 Abandoned
Array ( [id] => 15840413 [patent_doc_number] => 20200135489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE HAVING NITROGEN DIFFUSED THEREIN [patent_app_type] => utility [patent_app_number] => 16/176005 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176005 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176005
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE HAVING NITROGEN DIFFUSED THEREIN Oct 30, 2018 Pending
Array ( [id] => 15840527 [patent_doc_number] => 20200135546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => Method for Shrinking Openings in Forming Integrated Circuits [patent_app_type] => utility [patent_app_number] => 16/176116 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176116 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176116
Method for shrinking openings in forming integrated circuits Oct 30, 2018 Issued
Array ( [id] => 16354748 [patent_doc_number] => 10795255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Method of forming layout definition of semiconductor device [patent_app_type] => utility [patent_app_number] => 16/175858 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4103 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175858 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175858
Method of forming layout definition of semiconductor device Oct 30, 2018 Issued
Array ( [id] => 15840363 [patent_doc_number] => 20200135464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => METHODS AND APPARATUS FOR PATTERNING SUBSTRATES USING ASYMMETRIC PHYSICAL VAPOR DEPOSITION [patent_app_type] => utility [patent_app_number] => 16/175289 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175289 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175289
METHODS AND APPARATUS FOR PATTERNING SUBSTRATES USING ASYMMETRIC PHYSICAL VAPOR DEPOSITION Oct 29, 2018 Abandoned
Array ( [id] => 18639442 [patent_doc_number] => 11764062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Method of forming semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/175819 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 7016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175819 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175819
Method of forming semiconductor structure Oct 29, 2018 Issued
Array ( [id] => 14285765 [patent_doc_number] => 20190140167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => ANGLED SURFACE REMOVAL PROCESS AND STRUCTURE RELATING THERETO [patent_app_type] => utility [patent_app_number] => 16/175205 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175205 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175205
ANGLED SURFACE REMOVAL PROCESS AND STRUCTURE RELATING THERETO Oct 29, 2018 Pending
Array ( [id] => 17181537 [patent_doc_number] => 11158788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Atomic layer deposition and physical vapor deposition bilayer for additive patterning [patent_app_type] => utility [patent_app_number] => 16/175088 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4079 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 490 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175088 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175088
Atomic layer deposition and physical vapor deposition bilayer for additive patterning Oct 29, 2018 Issued
Array ( [id] => 18152412 [patent_doc_number] => 11565365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => System and method for monitoring chemical mechanical polishing [patent_app_type] => utility [patent_app_number] => 16/175778 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175778 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175778
System and method for monitoring chemical mechanical polishing Oct 29, 2018 Issued
Array ( [id] => 15841231 [patent_doc_number] => 20200135898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => HARD MASK REPLENISHMENT FOR ETCHING PROCESSES [patent_app_type] => utility [patent_app_number] => 16/175032 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175032 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175032
HARD MASK REPLENISHMENT FOR ETCHING PROCESSES Oct 29, 2018 Abandoned
Array ( [id] => 15841179 [patent_doc_number] => 20200135872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => SCALED GATE CONTACT AND SOURCE/DRAIN CAP [patent_app_type] => utility [patent_app_number] => 16/169269 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169269 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169269
Scaled gate contact and source/drain cap Oct 23, 2018 Issued
Array ( [id] => 15840699 [patent_doc_number] => 20200135632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => DIE ISOLATION ON A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/169843 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169843 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169843
DIE ISOLATION ON A SUBSTRATE Oct 23, 2018 Abandoned
Array ( [id] => 17122085 [patent_doc_number] => 11133226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => FUSI gated device formation [patent_app_type] => utility [patent_app_number] => 16/169220 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169220
FUSI gated device formation Oct 23, 2018 Issued
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