Search

Sophia T. Nguyen

Examiner (ID: 13973)

Most Active Art Unit
2822
Art Unit(s)
2893, 2822, 2821
Total Applications
655
Issued Applications
250
Pending Applications
133
Abandoned Applications
284

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16386475 [patent_doc_number] => 10811320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Footing removal in cut-metal process [patent_app_type] => utility [patent_app_number] => 15/966437 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966437 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/966437
Footing removal in cut-metal process Apr 29, 2018 Issued
Array ( [id] => 14137765 [patent_doc_number] => 20190103272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => Method for Manufacturing a Semiconductor Device [patent_app_type] => utility [patent_app_number] => 15/967480 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967480 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967480
Method for manufacturing a semiconductor device Apr 29, 2018 Issued
Array ( [id] => 13378851 [patent_doc_number] => 20180240967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => METHOD OF FORMING AN ON-PITCH SELF-ALIGNED HARD MASK FOR CONTACT TO A TUNNEL JUNCTION USING ION BEAM ETCHING [patent_app_type] => utility [patent_app_number] => 15/956376 [patent_app_country] => US [patent_app_date] => 2018-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5707 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15956376 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/956376
METHOD OF FORMING AN ON-PITCH SELF-ALIGNED HARD MASK FOR CONTACT TO A TUNNEL JUNCTION USING ION BEAM ETCHING Apr 17, 2018 Abandoned
Array ( [id] => 13963107 [patent_doc_number] => 20190057898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/954912 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15954912 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/954912
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE Apr 16, 2018 Abandoned
Array ( [id] => 13363935 [patent_doc_number] => 20180233507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES [patent_app_type] => utility [patent_app_number] => 15/950313 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950313 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950313
SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES Apr 10, 2018 Abandoned
Array ( [id] => 13320865 [patent_doc_number] => 20180211970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE WITH SELF-ALIGNED DRAIN SIDE SELECT GATE ELECTRODES AND METHOD OF MAKING THEREOF [patent_app_type] => utility [patent_app_number] => 15/927688 [patent_app_country] => US [patent_app_date] => 2018-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15927688 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/927688
Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof Mar 20, 2018 Issued
Array ( [id] => 14050073 [patent_doc_number] => 20190081144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/910582 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910582 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910582
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME Mar 1, 2018 Abandoned
Array ( [id] => 13528703 [patent_doc_number] => 20180315894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/909884 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909884 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909884
SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME Feb 28, 2018 Abandoned
Array ( [id] => 13514513 [patent_doc_number] => 20180308799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => FLEXIBLE ELECTRONIC CIRCUITS WITH EMBEDDED INTEGRATED CIRCUIT DIE AND METHODS OF MAKING AND USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/889009 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889009 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/889009
FLEXIBLE ELECTRONIC CIRCUITS WITH EMBEDDED INTEGRATED CIRCUIT DIE AND METHODS OF MAKING AND USING THE SAME Feb 4, 2018 Abandoned
Array ( [id] => 12849589 [patent_doc_number] => 20180175036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => Multi-Gate Device and Method of Fabrication Thereof [patent_app_type] => utility [patent_app_number] => 15/887347 [patent_app_country] => US [patent_app_date] => 2018-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887347 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/887347
Multi-gate device and method of fabrication thereof Feb 1, 2018 Issued
Array ( [id] => 12738280 [patent_doc_number] => 20180137927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => Three-Dimensional Vertical One-Time-Programmable Memory Comprising No Separate Diode Layer [patent_app_type] => utility [patent_app_number] => 15/870855 [patent_app_country] => US [patent_app_date] => 2018-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870855 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/870855
Three-Dimensional Vertical One-Time-Programmable Memory Comprising No Separate Diode Layer Jan 12, 2018 Abandoned
Array ( [id] => 12759946 [patent_doc_number] => 20180145150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => HIGH-K LAYER CHAMFERING TO PREVENT OXYGEN INGRESS IN REPLACEMENT METAL GATE (RMG) PROCESS [patent_app_type] => utility [patent_app_number] => 15/859340 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859340 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859340
HIGH-K LAYER CHAMFERING TO PREVENT OXYGEN INGRESS IN REPLACEMENT METAL GATE (RMG) PROCESS Dec 29, 2017 Abandoned
Array ( [id] => 14221375 [patent_doc_number] => 20190123072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => DISPLAY PANEL AND PIXEL CIRCUIT THEREOF [patent_app_type] => utility [patent_app_number] => 15/835463 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835463 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/835463
DISPLAY PANEL AND PIXEL CIRCUIT THEREOF Dec 7, 2017 Abandoned
Array ( [id] => 14317273 [patent_doc_number] => 20190148340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/835466 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835466 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/835466
Package structure and method of manufacturing the same Dec 7, 2017 Issued
Array ( [id] => 13629815 [patent_doc_number] => 20180366460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => ELECTROSTATIC DISCHARGE DEVICES [patent_app_type] => utility [patent_app_number] => 15/835396 [patent_app_country] => US [patent_app_date] => 2017-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835396 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/835396
Electrostatic discharge devices Dec 6, 2017 Issued
Array ( [id] => 14151707 [patent_doc_number] => 10256243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Semiconductor structure, static random access memory, and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 15/824830 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 10591 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824830 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824830
Semiconductor structure, static random access memory, and fabrication method thereof Nov 27, 2017 Issued
Array ( [id] => 15791931 [patent_doc_number] => 10629698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Method and structure for enabling high aspect ratio sacrificial gates [patent_app_type] => utility [patent_app_number] => 15/802095 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 7661 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802095 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802095
Method and structure for enabling high aspect ratio sacrificial gates Nov 1, 2017 Issued
Array ( [id] => 14801165 [patent_doc_number] => 10403592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Semiconductor packages and methods of packaging semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/726409 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 60 [patent_no_of_words] => 17191 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726409
Semiconductor packages and methods of packaging semiconductor devices Oct 5, 2017 Issued
Array ( [id] => 13996073 [patent_doc_number] => 20190067194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 15/692439 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692439 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/692439
Interconnect structure for semiconductor device and methods of fabrication thereof Aug 30, 2017 Issued
Array ( [id] => 12236076 [patent_doc_number] => 20180068939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'REDISTRIBUTION LAYER LINES' [patent_app_type] => utility [patent_app_number] => 15/677835 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677835 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/677835
REDISTRIBUTION LAYER LINES Aug 14, 2017 Abandoned
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