Sophia T. Nguyen

Array ( [id] => 10487119 [patent_doc_number] => 20150372139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'CONSTRAINING EPITAXIAL GROWTH ON FINS OF A FINFET DEVICE' [patent_app_type] => utility [patent_app_number] => 14/308003 [patent_app_country] => US [patent_app_date] => 2014-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14308003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10487087 [patent_doc_number] => 20150372107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'SEMICONDUCTOR DEVICES HAVING FINS, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FINS' [patent_app_type] => utility [patent_app_number] => 14/308014 [patent_app_country] => US [patent_app_date] => 2014-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8634 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14308014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10486916 [patent_doc_number] => 20150371936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 14/308369 [patent_app_country] => US [patent_app_date] => 2014-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14308369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9931546 [patent_doc_number] => 20150079738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'METHOD FOR PRODUCING TRENCH HIGH ELECTRON MOBILITY DEVICES' [patent_app_type] => utility [patent_app_number] => 14/307222 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8996 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14307222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10303009 [patent_doc_number] => 20150188009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/304817 [patent_app_country] => US [patent_app_date] => 2014-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2792 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14304817 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10277304 [patent_doc_number] => 20150162301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/276320 [patent_app_country] => US [patent_app_date] => 2014-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1684 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14276320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9783089 [patent_doc_number] => 20140299908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'LIGHT EMITTING DIODE PACKAGE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/267985 [patent_app_country] => US [patent_app_date] => 2014-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4765 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14267985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10329071 [patent_doc_number] => 20150214075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'MANUFACTURING METHOD OF SELECTIVE ELECTRONIC PACKAGING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/246114 [patent_app_country] => US [patent_app_date] => 2014-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2260 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14246114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11495646 [patent_doc_number] => 20170069831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'MAGNETIC DOMAIN WALL LOGIC DEVICES AND INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 15/119380 [patent_app_country] => US [patent_app_date] => 2014-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8955 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15119380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9909675 [patent_doc_number] => 20150064876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'SEPARATING DEVICE AND SEPARATING METHOD' [patent_app_type] => utility [patent_app_number] => 14/194612 [patent_app_country] => US [patent_app_date] => 2014-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14194612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10531160 [patent_doc_number] => 09257299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Method of manufacturing semiconductor device and semiconductor manufacturing apparatus' [patent_app_type] => utility [patent_app_number] => 14/192487 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3489 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14192487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10329327 [patent_doc_number] => 20150214331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'REPLACEMENT METAL GATE INCLUDING DIELECTRIC GATE MATERIAL' [patent_app_type] => utility [patent_app_number] => 14/168112 [patent_app_country] => US [patent_app_date] => 2014-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14168112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10329110 [patent_doc_number] => 20150214114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/166091 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11787542 [patent_doc_number] => 09397004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings' [patent_app_type] => utility [patent_app_number] => 14/164582 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5066 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14164582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10329112 [patent_doc_number] => 20150214116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'LOW LEAKAGE PMOS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/165107 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5806 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10329064 [patent_doc_number] => 20150214068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'METHOD OF PERFORMING ETCHING PROCESS' [patent_app_type] => utility [patent_app_number] => 14/162755 [patent_app_country] => US [patent_app_date] => 2014-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2499 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10321799 [patent_doc_number] => 20150206803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'METHOD OF FORMING INTER-LEVEL DIELECTRIC LAYER' [patent_app_type] => utility [patent_app_number] => 14/158857 [patent_app_country] => US [patent_app_date] => 2014-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3289 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10321790 [patent_doc_number] => 20150206794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'Method for Removing Micro Scratches In Chemical Mechanical Polishing Processes' [patent_app_type] => utility [patent_app_number] => 14/158593 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2636 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10321794 [patent_doc_number] => 20150206798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'Interconnect Structure And Method of Forming' [patent_app_type] => utility [patent_app_number] => 14/158483 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158483 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10321785 [patent_doc_number] => 20150206789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'METHOD OF MODIFYING POLYSILICON LAYER THROUGH NITROGEN INCORPORATION FOR ISOLATION STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/157855 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4591 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14157855 [rel_patent_id] =>[rel_patent_doc_number] =>)