
Sophia T. Nguyen
Examiner (ID: 13973)
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2893, 2822, 2821 |
| Total Applications | 655 |
| Issued Applications | 250 |
| Pending Applications | 133 |
| Abandoned Applications | 284 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10214367
[patent_doc_number] => 20150099359
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-09
[patent_title] => 'NOZZLE DESIGN FOR IMPROVED DISTRIBUTION OF REACTANTS FOR LARGE FORMAT SUBSTRATES'
[patent_app_type] => utility
[patent_app_number] => 14/045716
[patent_app_country] => US
[patent_app_date] => 2013-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 11236
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045716
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Array
(
[id] => 10208902
[patent_doc_number] => 20150093893
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-02
[patent_title] => 'PROCESS OF FORMING SEED LAYER IN VERTICAL TRENCH/VIA'
[patent_app_type] => utility
[patent_app_number] => 14/044855
[patent_app_country] => US
[patent_app_date] => 2013-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 1796
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Array
(
[id] => 10178834
[patent_doc_number] => 09209046
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-12-08
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/044490
[patent_app_country] => US
[patent_app_date] => 2013-10-02
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[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 6326
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/044490 | Semiconductor device and manufacturing method thereof | Oct 1, 2013 | Issued |
Array
(
[id] => 10202157
[patent_doc_number] => 20150087144
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-26
[patent_title] => 'APPARATUS AND METHOD OF MANUFACTURING METAL GATE SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/038091
[patent_app_country] => US
[patent_app_date] => 2013-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/038091 | APPARATUS AND METHOD OF MANUFACTURING METAL GATE SEMICONDUCTOR DEVICE | Sep 25, 2013 | Abandoned |
Array
(
[id] => 10464137
[patent_doc_number] => 20150349152
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[patent_kind] => A1
[patent_issue_date] => 2015-12-03
[patent_title] => 'METHOD FOR METALLIZATION OF SOLAR CELL SUBSTRATES'
[patent_app_type] => utility
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[patent_app_date] => 2013-08-15
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Array
(
[id] => 9188783
[patent_doc_number] => 20130328098
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[patent_kind] => A1
[patent_issue_date] => 2013-12-12
[patent_title] => 'BUFFER LAYER STRUCTURE FOR LIGHT-EMITTING DIODE'
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[patent_app_number] => 13/965649
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/965649 | BUFFER LAYER STRUCTURE FOR LIGHT-EMITTING DIODE | Aug 12, 2013 | Abandoned |
Array
(
[id] => 9864764
[patent_doc_number] => 20150044783
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[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'METHODS OF ALLEVIATING ADVERSE STRESS EFFECTS ON A WAFER, AND METHODS OF FORMING A SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/964544
[patent_app_country] => US
[patent_app_date] => 2013-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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Array
(
[id] => 9812639
[patent_doc_number] => 20150024584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-22
[patent_title] => 'METHODS FOR FORMING INTEGRATED CIRCUITS WITH REDUCED REPLACEMENT METAL GATE HEIGHT VARIABILITY'
[patent_app_type] => utility
[patent_app_number] => 13/943909
[patent_app_country] => US
[patent_app_date] => 2013-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4224
[patent_no_of_claims] => 20
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943909
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/943909 | METHODS FOR FORMING INTEGRATED CIRCUITS WITH REDUCED REPLACEMENT METAL GATE HEIGHT VARIABILITY | Jul 16, 2013 | Abandoned |
Array
(
[id] => 9805829
[patent_doc_number] => 20150017774
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-15
[patent_title] => 'METHOD OF FORMING FINS WITH RECESS SHAPES'
[patent_app_type] => utility
[patent_app_number] => 13/938786
[patent_app_country] => US
[patent_app_date] => 2013-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/938786 | METHOD OF FORMING FINS WITH RECESS SHAPES | Jul 9, 2013 | Abandoned |
Array
(
[id] => 9355227
[patent_doc_number] => 08673760
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-03-18
[patent_title] => 'Methods of forming structures on an integrated circuit product'
[patent_app_type] => utility
[patent_app_number] => 13/925200
[patent_app_country] => US
[patent_app_date] => 2013-06-24
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[patent_drawing_sheets_cnt] => 7
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Array
(
[id] => 10974880
[patent_doc_number] => 20140377915
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[patent_kind] => A1
[patent_issue_date] => 2014-12-25
[patent_title] => 'Pre-mold for a magnet semiconductor assembly group and method of producing the same'
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[patent_app_number] => 13/923191
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Array
(
[id] => 10015953
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[patent_title] => 'Distorting donor wafer to corresponding distortion of host wafer'
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Array
(
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Array
(
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[patent_title] => 'SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL WITH INSULATOR COATING'
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Array
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Array
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Array
(
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Array
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Array
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Array
(
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