Search

Sophia T. Nguyen

Examiner (ID: 13973)

Most Active Art Unit
2822
Art Unit(s)
2893, 2822, 2821
Total Applications
655
Issued Applications
250
Pending Applications
133
Abandoned Applications
284

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10214367 [patent_doc_number] => 20150099359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'NOZZLE DESIGN FOR IMPROVED DISTRIBUTION OF REACTANTS FOR LARGE FORMAT SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 14/045716 [patent_app_country] => US [patent_app_date] => 2013-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11236 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045716 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/045716
NOZZLE DESIGN FOR IMPROVED DISTRIBUTION OF REACTANTS FOR LARGE FORMAT SUBSTRATES Oct 2, 2013 Abandoned
Array ( [id] => 10208902 [patent_doc_number] => 20150093893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'PROCESS OF FORMING SEED LAYER IN VERTICAL TRENCH/VIA' [patent_app_type] => utility [patent_app_number] => 14/044855 [patent_app_country] => US [patent_app_date] => 2013-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1796 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14044855 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/044855
PROCESS OF FORMING SEED LAYER IN VERTICAL TRENCH/VIA Oct 1, 2013 Abandoned
Array ( [id] => 10178834 [patent_doc_number] => 09209046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/044490 [patent_app_country] => US [patent_app_date] => 2013-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 6326 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14044490 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/044490
Semiconductor device and manufacturing method thereof Oct 1, 2013 Issued
Array ( [id] => 10202157 [patent_doc_number] => 20150087144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'APPARATUS AND METHOD OF MANUFACTURING METAL GATE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/038091 [patent_app_country] => US [patent_app_date] => 2013-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14038091 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/038091
APPARATUS AND METHOD OF MANUFACTURING METAL GATE SEMICONDUCTOR DEVICE Sep 25, 2013 Abandoned
Array ( [id] => 10464137 [patent_doc_number] => 20150349152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'METHOD FOR METALLIZATION OF SOLAR CELL SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 14/427638 [patent_app_country] => US [patent_app_date] => 2013-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7502 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14427638 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/427638
METHOD FOR METALLIZATION OF SOLAR CELL SUBSTRATES Aug 14, 2013 Abandoned
Array ( [id] => 9188783 [patent_doc_number] => 20130328098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'BUFFER LAYER STRUCTURE FOR LIGHT-EMITTING DIODE' [patent_app_type] => utility [patent_app_number] => 13/965649 [patent_app_country] => US [patent_app_date] => 2013-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1904 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13965649 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/965649
BUFFER LAYER STRUCTURE FOR LIGHT-EMITTING DIODE Aug 12, 2013 Abandoned
Array ( [id] => 9864764 [patent_doc_number] => 20150044783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'METHODS OF ALLEVIATING ADVERSE STRESS EFFECTS ON A WAFER, AND METHODS OF FORMING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/964544 [patent_app_country] => US [patent_app_date] => 2013-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13964544 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/964544
METHODS OF ALLEVIATING ADVERSE STRESS EFFECTS ON A WAFER, AND METHODS OF FORMING A SEMICONDUCTOR DEVICE Aug 11, 2013 Abandoned
Array ( [id] => 9812639 [patent_doc_number] => 20150024584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'METHODS FOR FORMING INTEGRATED CIRCUITS WITH REDUCED REPLACEMENT METAL GATE HEIGHT VARIABILITY' [patent_app_type] => utility [patent_app_number] => 13/943909 [patent_app_country] => US [patent_app_date] => 2013-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943909 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943909
METHODS FOR FORMING INTEGRATED CIRCUITS WITH REDUCED REPLACEMENT METAL GATE HEIGHT VARIABILITY Jul 16, 2013 Abandoned
Array ( [id] => 9805829 [patent_doc_number] => 20150017774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'METHOD OF FORMING FINS WITH RECESS SHAPES' [patent_app_type] => utility [patent_app_number] => 13/938786 [patent_app_country] => US [patent_app_date] => 2013-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13938786 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/938786
METHOD OF FORMING FINS WITH RECESS SHAPES Jul 9, 2013 Abandoned
Array ( [id] => 9355227 [patent_doc_number] => 08673760 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-18 [patent_title] => 'Methods of forming structures on an integrated circuit product' [patent_app_type] => utility [patent_app_number] => 13/925200 [patent_app_country] => US [patent_app_date] => 2013-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 5039 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925200 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925200
Methods of forming structures on an integrated circuit product Jun 23, 2013 Issued
Array ( [id] => 10974880 [patent_doc_number] => 20140377915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'Pre-mold for a magnet semiconductor assembly group and method of producing the same' [patent_app_type] => utility [patent_app_number] => 13/923191 [patent_app_country] => US [patent_app_date] => 2013-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13923191 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/923191
Pre-mold for a magnet semiconductor assembly group and method of producing the same Jun 19, 2013 Abandoned
Array ( [id] => 10015953 [patent_doc_number] => 09058974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Distorting donor wafer to corresponding distortion of host wafer' [patent_app_type] => utility [patent_app_number] => 13/908510 [patent_app_country] => US [patent_app_date] => 2013-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4798 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13908510 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/908510
Distorting donor wafer to corresponding distortion of host wafer Jun 2, 2013 Issued
Array ( [id] => 9882420 [patent_doc_number] => 08969184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Method for fabricating a porous semiconductor body region' [patent_app_type] => utility [patent_app_number] => 13/903784 [patent_app_country] => US [patent_app_date] => 2013-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3196 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13903784 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/903784
Method for fabricating a porous semiconductor body region May 27, 2013 Issued
Array ( [id] => 9064877 [patent_doc_number] => 20130256633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL WITH INSULATOR COATING' [patent_app_type] => utility [patent_app_number] => 13/903890 [patent_app_country] => US [patent_app_date] => 2013-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13738 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13903890 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/903890
SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL WITH INSULATOR COATING May 27, 2013 Abandoned
Array ( [id] => 9178313 [patent_doc_number] => 20130320298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-05 [patent_title] => 'SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL WITH INSULATOR COATING' [patent_app_type] => utility [patent_app_number] => 13/903883 [patent_app_country] => US [patent_app_date] => 2013-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13737 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13903883 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/903883
SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL WITH INSULATOR COATING May 27, 2013 Abandoned
Array ( [id] => 9064877 [patent_doc_number] => 20130256633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL WITH INSULATOR COATING' [patent_app_type] => utility [patent_app_number] => 13/903890 [patent_app_country] => US [patent_app_date] => 2013-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13738 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13903890 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/903890
SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL WITH INSULATOR COATING May 27, 2013 Abandoned
Array ( [id] => 11411645 [patent_doc_number] => 09558957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Method for manufacturing a substrate provided with different active areas and with planar and three-dimensional transistors' [patent_app_type] => utility [patent_app_number] => 13/894890 [patent_app_country] => US [patent_app_date] => 2013-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 5642 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894890 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/894890
Method for manufacturing a substrate provided with different active areas and with planar and three-dimensional transistors May 14, 2013 Issued
Array ( [id] => 10939532 [patent_doc_number] => 20140342553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'Method for Forming Semiconductor Structure Having Opening' [patent_app_type] => utility [patent_app_number] => 13/893349 [patent_app_country] => US [patent_app_date] => 2013-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893349 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/893349
Method for Forming Semiconductor Structure Having Opening May 13, 2013 Abandoned
Array ( [id] => 10939474 [patent_doc_number] => 20140342495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'PREPARATION OF CIGS ABSORBER LAYERS USING COATED SEMICONDUCTOR NANOPARTICLE AND NANOWIRE NETWORKS' [patent_app_type] => utility [patent_app_number] => 13/893756 [patent_app_country] => US [patent_app_date] => 2013-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3161 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893756 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/893756
Preparation of CIGS absorber layers using coated semiconductor nanoparticle and nanowire networks May 13, 2013 Issued
Array ( [id] => 10939451 [patent_doc_number] => 20140342473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'SEMICONDUCTOR PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 13/894031 [patent_app_country] => US [patent_app_date] => 2013-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1326 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894031 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/894031
SEMICONDUCTOR PROCESSING METHOD May 13, 2013 Abandoned
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