Srirama T. Channavajjala

Array ( [id] => 18549448 [patent_doc_number] => 11722816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Signal processing circuit [patent_app_type] => utility [patent_app_number] => 17/526084 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4494 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19168971 [patent_doc_number] => 11984890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Scalable interconnected quantum architecture [patent_app_type] => utility [patent_app_number] => 17/525899 [patent_app_country] => US [patent_app_date] => 2021-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18913521 [patent_doc_number] => 11876516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Non-fighting level shifters [patent_app_type] => utility [patent_app_number] => 17/525345 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19063670 [patent_doc_number] => 11942933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Voltage level shifting with reduced timing degradation [patent_app_type] => utility [patent_app_number] => 17/521651 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 9657 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17969392 [patent_doc_number] => 11486916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Frequency synthesizer output cycle counter including ring encoder [patent_app_type] => utility [patent_app_number] => 17/515637 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19285373 [patent_doc_number] => 20240221850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SHIFT REGISTER AND DRIVING METHOD THEREFOR, GATE DRIVER CIRCUIT, AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/913617 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17913617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18001572 [patent_doc_number] => 11502690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-15 [patent_title] => Power supply generation for transmitter [patent_app_type] => utility [patent_app_number] => 17/512256 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17390250 [patent_doc_number] => 20220038102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => TERMINATION CALIBRATION SCHEME USING A CURRENT MIRROR [patent_app_type] => utility [patent_app_number] => 17/502741 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17861368 [patent_doc_number] => 11442524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-13 [patent_title] => Power management circuit and method [patent_app_type] => utility [patent_app_number] => 17/498321 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11954 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18292830 [patent_doc_number] => 11621706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Complementary clock gate and low power flip-flop circuit including same [patent_app_type] => utility [patent_app_number] => 17/496941 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5048 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17746283 [patent_doc_number] => 11394373 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-19 [patent_title] => Managing flip flop circuits [patent_app_type] => utility [patent_app_number] => 17/496291 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 11540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17979256 [patent_doc_number] => 11496136 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-08 [patent_title] => Clock generating circuit and a semiconductor system using the clock generating circuit [patent_app_type] => utility [patent_app_number] => 17/492965 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 16735 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18999692 [patent_doc_number] => 11916555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Flip-flop with internal circuit for generating inflated low and high pulse width signals [patent_app_type] => utility [patent_app_number] => 17/490241 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5581 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17490241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17848608 [patent_doc_number] => 11437997 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-06 [patent_title] => Level shifter circuit [patent_app_type] => utility [patent_app_number] => 17/491173 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 10446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17816979 [patent_doc_number] => 11422586 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-23 [patent_title] => Methods and systems for generation of balanced secondary clocks from root clock [patent_app_type] => utility [patent_app_number] => 17/488559 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4687 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18271644 [patent_doc_number] => 20230092886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => PHASE LOCK LOOP WITH AN ADAPTIVE LOOP FILTER [patent_app_type] => utility [patent_app_number] => 17/482015 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18863485 [patent_doc_number] => 20230417921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => PHOTODETECTION DEVICE AND PHOTODETECTION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/250282 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18250282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19428866 [patent_doc_number] => 12088306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Clock domain crossing [patent_app_type] => utility [patent_app_number] => 18/025155 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10039 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18025155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17758522 [patent_doc_number] => 11398825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-26 [patent_title] => Receiving device, control method of receiving device, and memory controller [patent_app_type] => utility [patent_app_number] => 17/410800 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17848607 [patent_doc_number] => 11437996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Dynamic control conversion circuit [patent_app_type] => utility [patent_app_number] => 17/408614 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5057 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408614 [rel_patent_id] =>[rel_patent_doc_number] =>)