Search

Srirama T. Channavajjala

Examiner (ID: 8544)

Most Active Art Unit
2157
Art Unit(s)
2157, 2154, 2164, 2771, 2177, 2158, 2777, 2166, 2161, 2776
Total Applications
1249
Issued Applications
847
Pending Applications
104
Abandoned Applications
304

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15233481 [patent_doc_number] => 10504469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Shift-buffer circuit, gate driving circuit, display panel and driving method [patent_app_type] => utility [patent_app_number] => 15/768948 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10076 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15768948 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/768948
Shift-buffer circuit, gate driving circuit, display panel and driving method Oct 16, 2017 Issued
Array ( [id] => 15233481 [patent_doc_number] => 10504469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Shift-buffer circuit, gate driving circuit, display panel and driving method [patent_app_type] => utility [patent_app_number] => 15/768948 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10076 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15768948 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/768948
Shift-buffer circuit, gate driving circuit, display panel and driving method Oct 16, 2017 Issued
Array ( [id] => 14023877 [patent_doc_number] => 20190073932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => SHIFT REGISTER UNIT, DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/762337 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15762337 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/762337
Shift register unit, driving method thereof, gate driving circuit and display device Oct 11, 2017 Issued
Array ( [id] => 13962643 [patent_doc_number] => 20190057666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => RESET CIRCUIT, SHIFT REGISTER CIRCUIT, GATE DRIVING CIRCUIT, DISPLAY APPARATUS, AND DRIVING METHOD [patent_app_type] => utility [patent_app_number] => 15/770904 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15770904 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/770904
Reset circuit, shift register circuit, gate driving circuit, display apparatus, and driving method Sep 28, 2017 Issued
Array ( [id] => 14135113 [patent_doc_number] => 20190101946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => Configuration of Voltage Regulation Circuitry [patent_app_type] => utility [patent_app_number] => 15/721509 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721509 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721509
Configuration of voltage regulation circuitry Sep 28, 2017 Issued
Array ( [id] => 15640489 [patent_doc_number] => 10593245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Shift register, gate driving circuit, display panel and driving method [patent_app_type] => utility [patent_app_number] => 15/761749 [patent_app_country] => US [patent_app_date] => 2017-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9191 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 998 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15761749 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/761749
Shift register, gate driving circuit, display panel and driving method Sep 19, 2017 Issued
Array ( [id] => 14334325 [patent_doc_number] => 10298195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Radio frequency filter employing notch structure [patent_app_type] => utility [patent_app_number] => 15/704014 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 4154 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704014 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704014
Radio frequency filter employing notch structure Sep 13, 2017 Issued
Array ( [id] => 13994821 [patent_doc_number] => 20190066568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => SHIFT REGISTER UNIT AND DRIVING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 15/765263 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15765263 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/765263
Shift register unit and driving method therefor Sep 7, 2017 Issued
Array ( [id] => 13998091 [patent_doc_number] => 20190068203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => SELF-CLOCKING SAMPLER WITH REDUCED METASTABILITY [patent_app_type] => utility [patent_app_number] => 15/693325 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693325 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693325
Self-clocking sampler with reduced metastability Aug 30, 2017 Issued
Array ( [id] => 14491341 [patent_doc_number] => 10332468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Gate driving circuit and driving method thereof [patent_app_type] => utility [patent_app_number] => 15/568220 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4830 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15568220 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/568220
Gate driving circuit and driving method thereof Aug 29, 2017 Issued
Array ( [id] => 13693055 [patent_doc_number] => 20170357482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => APPARATUSES AND METHODS FOR TIMING DOMAIN CROSSING [patent_app_type] => utility [patent_app_number] => 15/690085 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690085 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690085
Apparatuses and methods for timing domain crossing Aug 28, 2017 Issued
Array ( [id] => 15140969 [patent_doc_number] => 10483983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Clock generating circuit and signal processing device [patent_app_type] => utility [patent_app_number] => 15/683788 [patent_app_country] => US [patent_app_date] => 2017-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2882 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683788 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/683788
Clock generating circuit and signal processing device Aug 22, 2017 Issued
Array ( [id] => 13031599 [patent_doc_number] => 10038429 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-31 [patent_title] => High-speed soft-edge sense-amplifier-based flip-flop [patent_app_type] => utility [patent_app_number] => 15/683691 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5444 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683691 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/683691
High-speed soft-edge sense-amplifier-based flip-flop Aug 21, 2017 Issued
Array ( [id] => 13964261 [patent_doc_number] => 20190058475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => Level Shifter with Bypass Control [patent_app_type] => utility [patent_app_number] => 15/682327 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682327 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682327
Level shifter with bypass control Aug 20, 2017 Issued
Array ( [id] => 13964265 [patent_doc_number] => 20190058477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => HIGH-VOLTAGE TOLERANT LEVEL SHIFTER USING THIN-OXIDE TRANSISTORS AND A MIDDLE-OF-THE-LINE (MOL) CAPACITOR [patent_app_type] => utility [patent_app_number] => 15/680643 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680643 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/680643
High-voltage tolerant level shifter using thin-oxide transistors and a middle-of-the-line (MOL) capacitor Aug 17, 2017 Issued
Array ( [id] => 14012803 [patent_doc_number] => 10224885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Differential logic with low voltage supply [patent_app_type] => utility [patent_app_number] => 15/679869 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6655 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679869 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679869
Differential logic with low voltage supply Aug 16, 2017 Issued
Array ( [id] => 12517569 [patent_doc_number] => 10003328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-19 [patent_title] => Hybrid pulse-width control circuit with process and offset calibration [patent_app_type] => utility [patent_app_number] => 15/680120 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680120 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/680120
Hybrid pulse-width control circuit with process and offset calibration Aug 16, 2017 Issued
Array ( [id] => 16972045 [patent_doc_number] => 11068016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Output signal generation circuit [patent_app_type] => utility [patent_app_number] => 15/678153 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5500 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678153 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678153
Output signal generation circuit Aug 15, 2017 Issued
Array ( [id] => 16171208 [patent_doc_number] => 10712769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Method and apparatus for clock signal distribution [patent_app_type] => utility [patent_app_number] => 15/678811 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3385 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678811 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678811
Method and apparatus for clock signal distribution Aug 15, 2017 Issued
Array ( [id] => 13920927 [patent_doc_number] => 10204587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Shift register unit and drive method thereof, shift register and display apparatus [patent_app_type] => utility [patent_app_number] => 15/750417 [patent_app_country] => US [patent_app_date] => 2017-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6943 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15750417 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/750417
Shift register unit and drive method thereof, shift register and display apparatus Aug 13, 2017 Issued
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