Search

Srirama T. Channavajjala

Examiner (ID: 8544)

Most Active Art Unit
2157
Art Unit(s)
2157, 2154, 2164, 2771, 2177, 2158, 2777, 2166, 2161, 2776
Total Applications
1249
Issued Applications
847
Pending Applications
104
Abandoned Applications
304

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10531824 [patent_doc_number] => 09257973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-09 [patent_title] => 'Supply-state-enabled level shifter interface circuit and method' [patent_app_type] => utility [patent_app_number] => 14/532151 [patent_app_country] => US [patent_app_date] => 2014-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14532151 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/532151
Supply-state-enabled level shifter interface circuit and method Nov 3, 2014 Issued
Array ( [id] => 11776748 [patent_doc_number] => 09385733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Clock generating apparatus and fractional frequency divider thereof' [patent_app_type] => utility [patent_app_number] => 14/527779 [patent_app_country] => US [patent_app_date] => 2014-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6263 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14527779 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/527779
Clock generating apparatus and fractional frequency divider thereof Oct 29, 2014 Issued
Array ( [id] => 10158387 [patent_doc_number] => 09190170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-17 [patent_title] => 'Shift register unit, gate driving device, display panel and display device' [patent_app_type] => utility [patent_app_number] => 14/525160 [patent_app_country] => US [patent_app_date] => 2014-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 11617 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14525160 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/525160
Shift register unit, gate driving device, display panel and display device Oct 26, 2014 Issued
Array ( [id] => 11825460 [patent_doc_number] => 20170214397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'CLOCK DELAY ADJUSTING CIRCUIT BASED ON EDGE ADDITION AND INTEGRATED CHIP THEREOF' [patent_app_type] => utility [patent_app_number] => 15/313809 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15313809 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/313809
Clock delay adjusting circuit based on edge addition and integrated chip thereof Oct 19, 2014 Issued
Array ( [id] => 10463581 [patent_doc_number] => 20150348596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT, DRIVING METHOD AND DISPLAY APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/517001 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517001 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/517001
Shift register unit, gate driving circuit, driving method and display apparatus Oct 16, 2014 Issued
Array ( [id] => 10185257 [patent_doc_number] => 09214943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-15 [patent_title] => 'Fractional frequency divider' [patent_app_type] => utility [patent_app_number] => 14/516559 [patent_app_country] => US [patent_app_date] => 2014-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5113 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14516559 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/516559
Fractional frequency divider Oct 15, 2014 Issued
Array ( [id] => 10745412 [patent_doc_number] => 20160091563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'SCAN FLIP-FLOP' [patent_app_type] => utility [patent_app_number] => 14/501475 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501475 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501475
SCAN FLIP-FLOP Sep 29, 2014 Abandoned
Array ( [id] => 10625108 [patent_doc_number] => 09344066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Digital open loop duty cycle correction circuit' [patent_app_type] => utility [patent_app_number] => 14/501488 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5755 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501488 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501488
Digital open loop duty cycle correction circuit Sep 29, 2014 Issued
Array ( [id] => 10531823 [patent_doc_number] => 09257972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-09 [patent_title] => 'High speed dynamic flip-flop circuit with split output driver' [patent_app_type] => utility [patent_app_number] => 14/499409 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499409 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/499409
High speed dynamic flip-flop circuit with split output driver Sep 28, 2014 Issued
Array ( [id] => 9984522 [patent_doc_number] => 09030242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Data output timing control circuit for semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 14/495014 [patent_app_country] => US [patent_app_date] => 2014-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4763 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14495014 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/495014
Data output timing control circuit for semiconductor apparatus Sep 23, 2014 Issued
Array ( [id] => 9928972 [patent_doc_number] => 20150077164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'PLL FREQUENCY SYNTHESIZER WITH MULTI-CURVE VCO IMPLEMENTING CLOSED LOOP CURVE SEARCHING USING CHARGE PUMP CURRENT MODULATION' [patent_app_type] => utility [patent_app_number] => 14/494466 [patent_app_country] => US [patent_app_date] => 2014-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8255 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14494466 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/494466
PLL frequency synthesizer with multi-curve VCO implementing closed loop curve searching using charge pump current modulation Sep 22, 2014 Issued
Array ( [id] => 10531851 [patent_doc_number] => 09258000 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-09 [patent_title] => 'Combined lock/out-of-lock detector for phase locked loops' [patent_app_type] => utility [patent_app_number] => 14/493539 [patent_app_country] => US [patent_app_date] => 2014-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4499 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14493539 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/493539
Combined lock/out-of-lock detector for phase locked loops Sep 22, 2014 Issued
Array ( [id] => 9850994 [patent_doc_number] => 08952731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Voltage controlled switching element gate drive circuit' [patent_app_type] => utility [patent_app_number] => 14/489861 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 7745 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14489861 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/489861
Voltage controlled switching element gate drive circuit Sep 17, 2014 Issued
Array ( [id] => 9850994 [patent_doc_number] => 08952731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Voltage controlled switching element gate drive circuit' [patent_app_type] => utility [patent_app_number] => 14/489861 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 7745 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14489861 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/489861
Voltage controlled switching element gate drive circuit Sep 17, 2014 Issued
Array ( [id] => 9850994 [patent_doc_number] => 08952731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Voltage controlled switching element gate drive circuit' [patent_app_type] => utility [patent_app_number] => 14/489861 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 7745 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14489861 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/489861
Voltage controlled switching element gate drive circuit Sep 17, 2014 Issued
Array ( [id] => 9850994 [patent_doc_number] => 08952731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Voltage controlled switching element gate drive circuit' [patent_app_type] => utility [patent_app_number] => 14/489861 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 7745 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14489861 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/489861
Voltage controlled switching element gate drive circuit Sep 17, 2014 Issued
Array ( [id] => 10519436 [patent_doc_number] => 09246496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Semiconductor device, semiconductor system and method for operating semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/489157 [patent_app_country] => US [patent_app_date] => 2014-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6773 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14489157 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/489157
Semiconductor device, semiconductor system and method for operating semiconductor device Sep 16, 2014 Issued
Array ( [id] => 10371177 [patent_doc_number] => 20150256183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/487858 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8341 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487858 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/487858
Semiconductor device and semiconductor system including the same Sep 15, 2014 Issued
Array ( [id] => 10660300 [patent_doc_number] => 20160006444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'DIGITALLY CONTROLLED DELAY-LOCKED LOOP REFERENCE GENERATOR' [patent_app_type] => utility [patent_app_number] => 14/486694 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14486694 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/486694
DIGITALLY CONTROLLED DELAY-LOCKED LOOP REFERENCE GENERATOR Sep 14, 2014 Abandoned
Array ( [id] => 10652846 [patent_doc_number] => 09369118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Duty cycle correction circuit and semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/484908 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 14820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14484908 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/484908
Duty cycle correction circuit and semiconductor device Sep 11, 2014 Issued
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