Srirama T. Channavajjala

Array ( [id] => 9469928 [patent_doc_number] => 08723567 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-13 [patent_title] => 'Adjustable pole and zero location for a second order low pass filter used in a phase lock loop circuit' [patent_app_type] => utility [patent_app_number] => 13/666120 [patent_app_country] => US [patent_app_date] => 2012-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 5869 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13666120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9145935 [patent_doc_number] => 20130300458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'Clock Signal Synchronization Circuit' [patent_app_type] => utility [patent_app_number] => 13/616276 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1603 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13616276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9367968 [patent_doc_number] => 20140077841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'PHASE FREQUENCY DETECTOR' [patent_app_type] => utility [patent_app_number] => 13/617233 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7441 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13617233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9167509 [patent_doc_number] => 08593192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Semiconductor device and method for controlling flip-flop' [patent_app_type] => utility [patent_app_number] => 13/612626 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 15739 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13612626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8583539 [patent_doc_number] => 20130002360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/610003 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 24712 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9000913 [patent_doc_number] => 20130222037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'VOLTAGE LEVEL SHIFTER' [patent_app_type] => utility [patent_app_number] => 13/605987 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13605987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8863831 [patent_doc_number] => 20130147534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'MASTER SLAVE FLIP-FLOP WITH LOW POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 13/605984 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13605984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9220799 [patent_doc_number] => 20140015574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/603539 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5704 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13603539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9172150 [patent_doc_number] => 20130314135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'DELAY-LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 13/602242 [patent_app_country] => US [patent_app_date] => 2012-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4853 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13602242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8987552 [patent_doc_number] => 20130214833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'DATA OUTPUT TIMING CONTROL CIRCUIT FOR SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/601661 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13601661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9945118 [patent_doc_number] => 08994426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Method and systems for high-precision pulse-width modulation' [patent_app_type] => utility [patent_app_number] => 13/600933 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4218 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13600933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9000912 [patent_doc_number] => 20130222036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'VOLTAGE LEVEL CONVERTING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/600130 [patent_app_country] => US [patent_app_date] => 2012-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5212 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13600130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8681547 [patent_doc_number] => 20130049831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'POLYPHASE CLOCK GENERATOR' [patent_app_type] => utility [patent_app_number] => 13/592831 [patent_app_country] => US [patent_app_date] => 2012-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8390 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13592831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9274210 [patent_doc_number] => 08638146 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-28 [patent_title] => 'Dual mode phase detection' [patent_app_type] => utility [patent_app_number] => 13/562770 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4994 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13562770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8481318 [patent_doc_number] => 20120280725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'DRIVER CIRCUIT, DISPLAY DEVICE INCLUDING THE DRIVER CIRCUIT, AND ELECTRONIC APPLIANCE INCLUDING THE DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/552986 [patent_app_country] => US [patent_app_date] => 2012-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10884 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13552986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9287087 [patent_doc_number] => 08643422 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-04 [patent_title] => 'Slicer and method of operating the same' [patent_app_type] => utility [patent_app_number] => 13/547396 [patent_app_country] => US [patent_app_date] => 2012-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6877 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13547396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8635294 [patent_doc_number] => 20130027097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'System Including Circuitry Providing Multiple Circuit Paths For Controlling A Characteristic of A Period Signal' [patent_app_type] => utility [patent_app_number] => 13/543971 [patent_app_country] => US [patent_app_date] => 2012-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12515 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13543971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8969451 [patent_doc_number] => 08508270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-13 [patent_title] => 'System and method for adjusting a characteristic of a periodic signal with use of a filtered bias voltage' [patent_app_type] => utility [patent_app_number] => 13/544001 [patent_app_country] => US [patent_app_date] => 2012-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 12406 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13544001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8583498 [patent_doc_number] => 20130002319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'Frequency Divider and Phase Locked Loop Including the Same' [patent_app_type] => utility [patent_app_number] => 13/535424 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8847032 [patent_doc_number] => 08456219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'H bridge driver circuit' [patent_app_type] => utility [patent_app_number] => 13/533638 [patent_app_country] => US [patent_app_date] => 2012-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3490 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13533638 [rel_patent_id] =>[rel_patent_doc_number] =>)