Search

Srirama T. Channavajjala

Examiner (ID: 8544)

Most Active Art Unit
2157
Art Unit(s)
2157, 2154, 2164, 2771, 2177, 2158, 2777, 2166, 2161, 2776
Total Applications
1249
Issued Applications
847
Pending Applications
104
Abandoned Applications
304

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8451282 [patent_doc_number] => 20120262228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'CURRENT-MODE ANALOG BASEBAND APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/530126 [patent_app_country] => US [patent_app_date] => 2012-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11019 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13530126 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/530126
Current-mode analog baseband apparatus Jun 21, 2012 Issued
Array ( [id] => 9189279 [patent_doc_number] => 20130328594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'Divider, Method for Providing an Output Signal and Edge Tracker' [patent_app_type] => utility [patent_app_number] => 13/493501 [patent_app_country] => US [patent_app_date] => 2012-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12459 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13493501 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/493501
Divider, method for providing an output signal and edge tracker Jun 10, 2012 Issued
Array ( [id] => 8665265 [patent_doc_number] => 08378728 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-19 [patent_title] => 'Level shifting flip-flop' [patent_app_type] => utility [patent_app_number] => 13/487243 [patent_app_country] => US [patent_app_date] => 2012-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5821 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 621 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13487243 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/487243
Level shifting flip-flop Jun 2, 2012 Issued
Array ( [id] => 8403646 [patent_doc_number] => 20120235716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'ENHANCEMENT OF POWER MANAGEMENT USING DYNAMIC VOLTAGE AND FREQUENCY SCALING AND DIGITAL PHASE LOCK LOOP HIGH SPEED BYPASS MODE' [patent_app_type] => utility [patent_app_number] => 13/484472 [patent_app_country] => US [patent_app_date] => 2012-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13484472 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/484472
Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode May 30, 2012 Issued
Array ( [id] => 8500216 [patent_doc_number] => 20120299624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'VOLTAGE CONTROLLED SWITCHING ELEMENT GATE DRIVE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/480441 [patent_app_country] => US [patent_app_date] => 2012-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13480441 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/480441
Voltage controlled switching element gate drive circuit May 23, 2012 Issued
Array ( [id] => 8391342 [patent_doc_number] => 20120229186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'MEMORY INTERFACE CIRCUIT AND DRIVE CAPABILITY ADJUSTMENT METHOD FOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/474154 [patent_app_country] => US [patent_app_date] => 2012-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8913 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13474154 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/474154
Memory interface circuit and drive capability adjustment method for memory device May 16, 2012 Issued
Array ( [id] => 8705906 [patent_doc_number] => 20130063195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'DIGITAL INPUT BUFFER' [patent_app_type] => utility [patent_app_number] => 13/467256 [patent_app_country] => US [patent_app_date] => 2012-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13467256 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/467256
DIGITAL INPUT BUFFER May 8, 2012 Abandoned
Array ( [id] => 9118798 [patent_doc_number] => 20130285720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'MULTIPLE CHANNEL PHASE DETECTION' [patent_app_type] => utility [patent_app_number] => 13/456574 [patent_app_country] => US [patent_app_date] => 2012-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3025 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13456574 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/456574
MULTIPLE CHANNEL PHASE DETECTION Apr 25, 2012 Abandoned
Array ( [id] => 9928970 [patent_doc_number] => 20150077163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'DYNAMIC FREQUENCY DIVIDER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/394116 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4924 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14394116 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/394116
Dynamic frequency divider circuit Apr 19, 2012 Issued
Array ( [id] => 8410925 [patent_doc_number] => 08274324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-25 [patent_title] => 'Electrostatic actuator apparatus' [patent_app_type] => utility [patent_app_number] => 13/444953 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 6280 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13444953 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/444953
Electrostatic actuator apparatus Apr 11, 2012 Issued
Array ( [id] => 8310968 [patent_doc_number] => 20120187993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'Semiconductor Integrated Circuit and Control Method for Clock Signal Synchronization' [patent_app_type] => utility [patent_app_number] => 13/438050 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 18891 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438050 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/438050
Semiconductor integrated circuit and control method for clock signal synchronization Apr 2, 2012 Issued
Array ( [id] => 9065737 [patent_doc_number] => 20130257493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'LATCH WITH A FEEDBACK CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/436106 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7026 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13436106 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/436106
Latch with a feedback circuit Mar 29, 2012 Issued
Array ( [id] => 8288835 [patent_doc_number] => 20120177162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'Symmetric Phase Detector' [patent_app_type] => utility [patent_app_number] => 13/424728 [patent_app_country] => US [patent_app_date] => 2012-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4559 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13424728 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/424728
Symmetric Phase Detector Mar 19, 2012 Abandoned
Array ( [id] => 9350905 [patent_doc_number] => 08669800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Implementing power saving self powering down latch structure' [patent_app_type] => utility [patent_app_number] => 13/404096 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13404096 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/404096
Implementing power saving self powering down latch structure Feb 23, 2012 Issued
Array ( [id] => 8447000 [patent_doc_number] => 08289057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Phase locked loop' [patent_app_type] => utility [patent_app_number] => 13/351745 [patent_app_country] => US [patent_app_date] => 2012-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 35 [patent_no_of_words] => 24684 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 915 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13351745 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/351745
Phase locked loop Jan 16, 2012 Issued
Array ( [id] => 8310955 [patent_doc_number] => 20120187986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'LATCH CIRCUIT, CDR CIRCUIT, AND RECEIVER' [patent_app_type] => utility [patent_app_number] => 13/349195 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4717 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13349195 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/349195
LATCH CIRCUIT, CDR CIRCUIT, AND RECEIVER Jan 11, 2012 Abandoned
Array ( [id] => 8167495 [patent_doc_number] => 20120105140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/342620 [patent_app_country] => US [patent_app_date] => 2012-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15487 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20120105140.pdf [firstpage_image] =>[orig_patent_app_number] => 13342620 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/342620
VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY USING THE SAME Jan 2, 2012 Abandoned
Array ( [id] => 9317528 [patent_doc_number] => 20140049866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'Method for Controlling a Transistor and Control Circuit' [patent_app_type] => utility [patent_app_number] => 13/984268 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13984268 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/984268
Method for controlling a transistor and control circuit Dec 19, 2011 Issued
Array ( [id] => 8190719 [patent_doc_number] => 08183902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Methods and systems for digital pulse width modulator' [patent_app_type] => utility [patent_app_number] => 13/301175 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4592 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/183/08183902.pdf [firstpage_image] =>[orig_patent_app_number] => 13301175 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/301175
Methods and systems for digital pulse width modulator Nov 20, 2011 Issued
Array ( [id] => 8181018 [patent_doc_number] => 20120112805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'PHASE-FREQUENCY DETECTOR' [patent_app_type] => utility [patent_app_number] => 13/293280 [patent_app_country] => US [patent_app_date] => 2011-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4174 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20120112805.pdf [firstpage_image] =>[orig_patent_app_number] => 13293280 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/293280
PHASE-FREQUENCY DETECTOR Nov 9, 2011 Abandoned
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