Srirama T. Channavajjala

Array ( [id] => 8583504 [patent_doc_number] => 20130002325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'CONSTANT SWITCHING CURRENT FLIP-FLOP' [patent_app_type] => utility [patent_app_number] => 13/170402 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5657 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13170402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7507544 [patent_doc_number] => 20110254606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'Frequency Divider, Frequency Dividing Method Thereof, and Phase Locked Loop Utilizing the Frequency Divider' [patent_app_type] => utility [patent_app_number] => 13/169026 [patent_app_country] => US [patent_app_date] => 2011-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3702 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20110254606.pdf [firstpage_image] =>[orig_patent_app_number] => 13169026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7707363 [patent_doc_number] => 20120001664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'CLOCK DIVIDER CIRCUIT AND SYSTEM LSI HAVING SAME' [patent_app_type] => utility [patent_app_number] => 13/168378 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5224 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13168378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7707363 [patent_doc_number] => 20120001664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'CLOCK DIVIDER CIRCUIT AND SYSTEM LSI HAVING SAME' [patent_app_type] => utility [patent_app_number] => 13/168378 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5224 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13168378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7707363 [patent_doc_number] => 20120001664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'CLOCK DIVIDER CIRCUIT AND SYSTEM LSI HAVING SAME' [patent_app_type] => utility [patent_app_number] => 13/168378 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5224 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13168378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7707363 [patent_doc_number] => 20120001664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'CLOCK DIVIDER CIRCUIT AND SYSTEM LSI HAVING SAME' [patent_app_type] => utility [patent_app_number] => 13/168378 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5224 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13168378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7773762 [patent_doc_number] => 20120038402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'Clock generation circuit and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 13/067657 [patent_app_country] => US [patent_app_date] => 2011-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9936 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20120038402.pdf [firstpage_image] =>[orig_patent_app_number] => 13067657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8520341 [patent_doc_number] => 20120319750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'MULTI-PART CLOCK MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 13/163605 [patent_app_country] => US [patent_app_date] => 2011-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4100 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13163605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8514264 [patent_doc_number] => 20120313673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'FREQUENCY DIVIDER WITH RETIMED CONTROL SIGNAL AND RELATED FREQUENCY DIVIDING METHOD' [patent_app_type] => utility [patent_app_number] => 13/158482 [patent_app_country] => US [patent_app_date] => 2011-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13158482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7660601 [patent_doc_number] => 20110309870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'METHOD AND CONFIGURATION FOR GENERATING HIGH-ENERGY MICROWAVE PULSES' [patent_app_type] => utility [patent_app_number] => 13/155424 [patent_app_country] => US [patent_app_date] => 2011-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2702 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20110309870.pdf [firstpage_image] =>[orig_patent_app_number] => 13155424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7796548 [patent_doc_number] => 08125256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Bias generator providing for low power, self-biased delay element and delay line' [patent_app_type] => utility [patent_app_number] => 13/152478 [patent_app_country] => US [patent_app_date] => 2011-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 15708 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125256.pdf [firstpage_image] =>[orig_patent_app_number] => 13152478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8275500 [patent_doc_number] => 20120169378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'DIFFERENTIAL DATA SENSING' [patent_app_type] => utility [patent_app_number] => 13/118858 [patent_app_country] => US [patent_app_date] => 2011-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13118858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7667329 [patent_doc_number] => 20110316598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'APPARATUS AND METHOD FOR MODELING COARSE STEPSIZE DELAY ELEMENT AND DELAY LOCKED LOOP USING SAME' [patent_app_type] => utility [patent_app_number] => 13/117934 [patent_app_country] => US [patent_app_date] => 2011-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6000 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13117934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8329381 [patent_doc_number] => 08237477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-07 [patent_title] => 'Programmable clock generator used in dynamic-voltage-and-frequency-scaling (DVFS) operated in sub- and near- threshold region' [patent_app_type] => utility [patent_app_number] => 13/067232 [patent_app_country] => US [patent_app_date] => 2011-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3965 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13067232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8091131 [patent_doc_number] => 20120081171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'SWITCHING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/108013 [patent_app_country] => US [patent_app_date] => 2011-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4370 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20120081171.pdf [firstpage_image] =>[orig_patent_app_number] => 13108013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7739584 [patent_doc_number] => 20120019305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'HARMONIC REJECTION OF SIGNAL CONVERTING DEVICE AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/103102 [patent_app_country] => US [patent_app_date] => 2011-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6258 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20120019305.pdf [firstpage_image] =>[orig_patent_app_number] => 13103102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8474981 [patent_doc_number] => 20120274388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'SWITCHING ELEMENT HAVING AN ELECTROMECHANICAL SWITCH AND METHODS FOR MAKING AND USING SAME' [patent_app_type] => utility [patent_app_number] => 13/097513 [patent_app_country] => US [patent_app_date] => 2011-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4697 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13097513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6059456 [patent_doc_number] => 20110199139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'FLIP-FLOP CIRCUIT WITH INTERNAL LEVEL SHIFTER' [patent_app_type] => utility [patent_app_number] => 13/097054 [patent_app_country] => US [patent_app_date] => 2011-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3433 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20110199139.pdf [firstpage_image] =>[orig_patent_app_number] => 13097054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8474970 [patent_doc_number] => 20120274377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'SINGLE-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/095641 [patent_app_country] => US [patent_app_date] => 2011-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4552 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13095641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8463011 [patent_doc_number] => 20120268178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'Fully differential adaptive bandwidth PLL with differential supply regulation' [patent_app_type] => utility [patent_app_number] => 13/066731 [patent_app_country] => US [patent_app_date] => 2011-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13066731 [rel_patent_id] =>[rel_patent_doc_number] =>)