Search

Srirama T. Channavajjala

Examiner (ID: 8544)

Most Active Art Unit
2157
Art Unit(s)
2157, 2154, 2164, 2771, 2177, 2158, 2777, 2166, 2161, 2776
Total Applications
1249
Issued Applications
847
Pending Applications
104
Abandoned Applications
304

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6076237 [patent_doc_number] => 20110140764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'CMOS SWITCH FOR USE IN RADIO FREQUENCY SWITCHING AND ISOLATION ENHANCEMENT METHOD' [patent_app_type] => utility [patent_app_number] => 12/771567 [patent_app_country] => US [patent_app_date] => 2010-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20110140764.pdf [firstpage_image] =>[orig_patent_app_number] => 12771567 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/771567
CMOS SWITCH FOR USE IN RADIO FREQUENCY SWITCHING AND ISOLATION ENHANCEMENT METHOD Apr 29, 2010 Abandoned
Array ( [id] => 6011489 [patent_doc_number] => 20110221489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'AUTOMATIC FREQUENCY CALIBRATION CIRCUIT AND AUTOMATIC FREQUENCY CALIBRATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/767813 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5102 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20110221489.pdf [firstpage_image] =>[orig_patent_app_number] => 12767813 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/767813
Automatic frequency calibration circuit and automatic frequency calibration method Apr 26, 2010 Issued
Array ( [id] => 6539297 [patent_doc_number] => 20100271083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'FLIP-FLOP CIRCUIT AND PRESCALER CIRCUIT INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/765601 [patent_app_country] => US [patent_app_date] => 2010-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5738 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20100271083.pdf [firstpage_image] =>[orig_patent_app_number] => 12765601 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/765601
Flip-flop circuit and prescaler circuit including the same Apr 21, 2010 Issued
Array ( [id] => 5956606 [patent_doc_number] => 20110181336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'Output Buffer Circuit and Method for Avoiding Voltage Overshoot' [patent_app_type] => utility [patent_app_number] => 12/750671 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3058 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20110181336.pdf [firstpage_image] =>[orig_patent_app_number] => 12750671 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/750671
Output buffer circuit and method for avoiding voltage overshoot Mar 29, 2010 Issued
Array ( [id] => 7796542 [patent_doc_number] => 08125250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Frequency detection mechanism for a clock generation circuit' [patent_app_type] => utility [patent_app_number] => 12/732959 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125250.pdf [firstpage_image] =>[orig_patent_app_number] => 12732959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/732959
Frequency detection mechanism for a clock generation circuit Mar 25, 2010 Issued
Array ( [id] => 7482324 [patent_doc_number] => 20110234272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'METHOD AND APPARATUS FOR CHARGE PUMP LINEARIZATION IN FRACTIONAL-N PLLS' [patent_app_type] => utility [patent_app_number] => 12/732024 [patent_app_country] => US [patent_app_date] => 2010-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4441 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20110234272.pdf [firstpage_image] =>[orig_patent_app_number] => 12732024 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/732024
Method and apparatus for charge pump linearization in fractional-N PLLs Mar 24, 2010 Issued
Array ( [id] => 7796541 [patent_doc_number] => 08125249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Frequency measuring circuit and semiconductor device having the same' [patent_app_type] => utility [patent_app_number] => 12/661668 [patent_app_country] => US [patent_app_date] => 2010-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7600 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125249.pdf [firstpage_image] =>[orig_patent_app_number] => 12661668 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/661668
Frequency measuring circuit and semiconductor device having the same Mar 21, 2010 Issued
Array ( [id] => 8178736 [patent_doc_number] => 08179173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Digitally calibrated high speed clock distribution' [patent_app_type] => utility [patent_app_number] => 12/723285 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3866 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/179/08179173.pdf [firstpage_image] =>[orig_patent_app_number] => 12723285 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/723285
Digitally calibrated high speed clock distribution Mar 11, 2010 Issued
Array ( [id] => 6512200 [patent_doc_number] => 20100219865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'FREQUENCY DETECTION APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/712806 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20100219865.pdf [firstpage_image] =>[orig_patent_app_number] => 12712806 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712806
Frequency detection apparatus and method Feb 24, 2010 Issued
Array ( [id] => 7577856 [patent_doc_number] => 20110291738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'JFET Series Connection' [patent_app_type] => utility [patent_app_number] => 13/144085 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291738.pdf [firstpage_image] =>[orig_patent_app_number] => 13144085 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/144085
JFET series connection Feb 2, 2010 Issued
Array ( [id] => 7698967 [patent_doc_number] => 20110227623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'DUTY CYCLE CORRECTING CIRCUIT AND DUTY CYCLE CORRECTING METHOD' [patent_app_type] => utility [patent_app_number] => 12/687985 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7299 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20110227623.pdf [firstpage_image] =>[orig_patent_app_number] => 12687985 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/687985
Duty cycle correcting circuit and duty cycle correcting method Jan 14, 2010 Issued
Array ( [id] => 8544239 [patent_doc_number] => 08319534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Phase-locked loop' [patent_app_type] => utility [patent_app_number] => 13/147615 [patent_app_country] => US [patent_app_date] => 2010-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5444 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13147615 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/147615
Phase-locked loop Jan 10, 2010 Issued
Array ( [id] => 4458113 [patent_doc_number] => 07893735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Reset circuit and system having reset circuit' [patent_app_type] => utility [patent_app_number] => 12/646880 [patent_app_country] => US [patent_app_date] => 2009-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 15500 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/893/07893735.pdf [firstpage_image] =>[orig_patent_app_number] => 12646880 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/646880
Reset circuit and system having reset circuit Dec 22, 2009 Issued
Array ( [id] => 8283591 [patent_doc_number] => 08217691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Low power clocking scheme for a pipelined ADC' [patent_app_type] => utility [patent_app_number] => 12/645165 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2699 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12645165 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/645165
Low power clocking scheme for a pipelined ADC Dec 21, 2009 Issued
Array ( [id] => 5964549 [patent_doc_number] => 20110148480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'Divider with Enhanced Duty Cycle for Precision Oscillator Clocking Sources' [patent_app_type] => utility [patent_app_number] => 12/640189 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3649 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20110148480.pdf [firstpage_image] =>[orig_patent_app_number] => 12640189 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/640189
Divider with Enhanced Duty Cycle for Precision Oscillator Clocking Sources Dec 16, 2009 Abandoned
Array ( [id] => 6209183 [patent_doc_number] => 20110133809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'Semiconductor device and method for cancelling offset voltage of sense amplifier' [patent_app_type] => utility [patent_app_number] => 12/591884 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8143 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20110133809.pdf [firstpage_image] =>[orig_patent_app_number] => 12591884 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591884
Semiconductor device and method for cancelling offset voltage of sense amplifier Dec 2, 2009 Abandoned
Array ( [id] => 6209146 [patent_doc_number] => 20110133793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'CLOCK DIVIDER WITH SEAMLESS CLOCK FREQUENCY CHANGE' [patent_app_type] => utility [patent_app_number] => 12/630610 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20110133793.pdf [firstpage_image] =>[orig_patent_app_number] => 12630610 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630610
CLOCK DIVIDER WITH SEAMLESS CLOCK FREQUENCY CHANGE Dec 2, 2009 Abandoned
Array ( [id] => 6021968 [patent_doc_number] => 20110050294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/630443 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10482 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20110050294.pdf [firstpage_image] =>[orig_patent_app_number] => 12630443 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630443
Semiconductor memory device having a clock alignment training circuit and method for operating the same Dec 2, 2009 Issued
Array ( [id] => 4614750 [patent_doc_number] => 07990194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Apparatus and method for correcting duty cycle of clock signal' [patent_app_type] => utility [patent_app_number] => 12/630400 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3114 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/990/07990194.pdf [firstpage_image] =>[orig_patent_app_number] => 12630400 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630400
Apparatus and method for correcting duty cycle of clock signal Dec 2, 2009 Issued
Array ( [id] => 6021969 [patent_doc_number] => 20110050295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/630518 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5539 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20110050295.pdf [firstpage_image] =>[orig_patent_app_number] => 12630518 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630518
Semiconductor device having auto clock alignment training mode circuit Dec 2, 2009 Issued
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