Search

Srirama T. Channavajjala

Examiner (ID: 8544)

Most Active Art Unit
2157
Art Unit(s)
2157, 2154, 2164, 2771, 2177, 2158, 2777, 2166, 2161, 2776
Total Applications
1249
Issued Applications
847
Pending Applications
104
Abandoned Applications
304

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8458825 [patent_doc_number] => 08294497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Low-offset charge pump, duty cycle stabilizer, and delay locked loop' [patent_app_type] => utility [patent_app_number] => 12/629634 [patent_app_country] => US [patent_app_date] => 2009-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6159 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12629634 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/629634
Low-offset charge pump, duty cycle stabilizer, and delay locked loop Dec 1, 2009 Issued
Array ( [id] => 4625017 [patent_doc_number] => 08004319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Programmable clock divider' [patent_app_type] => utility [patent_app_number] => 12/627276 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004319.pdf [firstpage_image] =>[orig_patent_app_number] => 12627276 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/627276
Programmable clock divider Nov 29, 2009 Issued
Array ( [id] => 6225888 [patent_doc_number] => 20100182063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'FLIP-FLOP CIRCUIT WITH INTERNAL LEVEL SHIFTER' [patent_app_type] => utility [patent_app_number] => 12/624360 [patent_app_country] => US [patent_app_date] => 2009-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3433 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20100182063.pdf [firstpage_image] =>[orig_patent_app_number] => 12624360 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/624360
Flip-flop circuit with internal level shifter Nov 22, 2009 Issued
Array ( [id] => 7776143 [patent_doc_number] => 08120401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Methods and systems for digital pulse width modulator' [patent_app_type] => utility [patent_app_number] => 12/622511 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4570 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120401.pdf [firstpage_image] =>[orig_patent_app_number] => 12622511 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/622511
Methods and systems for digital pulse width modulator Nov 19, 2009 Issued
Array ( [id] => 7811860 [patent_doc_number] => 08134392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Phase locked loop' [patent_app_type] => utility [patent_app_number] => 12/622604 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 35 [patent_no_of_words] => 24667 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 708 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/134/08134392.pdf [firstpage_image] =>[orig_patent_app_number] => 12622604 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/622604
Phase locked loop Nov 19, 2009 Issued
Array ( [id] => 6568530 [patent_doc_number] => 20100060347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'BIAS GENERATOR PROVIDING FOR LOW POWER, SELF-BIASED DELAY ELEMENT AND DELAY LINE' [patent_app_type] => utility [patent_app_number] => 12/621983 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15686 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20100060347.pdf [firstpage_image] =>[orig_patent_app_number] => 12621983 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/621983
Bias generator providing for low power, self-biased delay element and delay line Nov 18, 2009 Issued
Array ( [id] => 6011472 [patent_doc_number] => 20110221476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => ' PHASE FREQUENCY DETECTOR' [patent_app_type] => utility [patent_app_number] => 13/130518 [patent_app_country] => US [patent_app_date] => 2009-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3112 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20110221476.pdf [firstpage_image] =>[orig_patent_app_number] => 13130518 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/130518
Phase frequency detector Nov 15, 2009 Issued
Array ( [id] => 6522286 [patent_doc_number] => 20100123499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'INFORMATION SYSTEM, SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/619396 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4924 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20100123499.pdf [firstpage_image] =>[orig_patent_app_number] => 12619396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/619396
INFORMATION SYSTEM, SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR Nov 15, 2009 Abandoned
Array ( [id] => 4451790 [patent_doc_number] => 07965115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Soft reference switch for phase locked loop' [patent_app_type] => utility [patent_app_number] => 12/617347 [patent_app_country] => US [patent_app_date] => 2009-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1961 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/965/07965115.pdf [firstpage_image] =>[orig_patent_app_number] => 12617347 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/617347
Soft reference switch for phase locked loop Nov 11, 2009 Issued
Array ( [id] => 5949563 [patent_doc_number] => 20110032011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'AUTO FREQUENCY CALIBRATOR, METHOD THEREOF AND FREQUENCY SYNTHESIZER USING IT' [patent_app_type] => utility [patent_app_number] => 12/617151 [patent_app_country] => US [patent_app_date] => 2009-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4358 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20110032011.pdf [firstpage_image] =>[orig_patent_app_number] => 12617151 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/617151
AUTO FREQUENCY CALIBRATOR, METHOD THEREOF AND FREQUENCY SYNTHESIZER USING IT Nov 11, 2009 Abandoned
Array ( [id] => 8190713 [patent_doc_number] => 08183899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Semiconductor integrated circuit and control method for clock signal synchronization' [patent_app_type] => utility [patent_app_number] => 12/615607 [patent_app_country] => US [patent_app_date] => 2009-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 39 [patent_no_of_words] => 18858 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/183/08183899.pdf [firstpage_image] =>[orig_patent_app_number] => 12615607 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/615607
Semiconductor integrated circuit and control method for clock signal synchronization Nov 9, 2009 Issued
Array ( [id] => 6475161 [patent_doc_number] => 20100207671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'FREQUENCY DIVIDING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/614508 [patent_app_country] => US [patent_app_date] => 2009-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2808 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20100207671.pdf [firstpage_image] =>[orig_patent_app_number] => 12614508 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/614508
Frequency dividing circuit Nov 8, 2009 Issued
Array ( [id] => 6052996 [patent_doc_number] => 20110109356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'APERTURE GENERATING CIRCUIT FOR A MULTIPLYING DELAY-LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 12/613936 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20110109356.pdf [firstpage_image] =>[orig_patent_app_number] => 12613936 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613936
Aperture generating circuit for a multiplying delay-locked loop Nov 5, 2009 Issued
Array ( [id] => 7796546 [patent_doc_number] => 08125254 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-28 [patent_title] => 'Techniques for configuring multi-path feedback loops' [patent_app_type] => utility [patent_app_number] => 12/613465 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6072 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125254.pdf [firstpage_image] =>[orig_patent_app_number] => 12613465 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613465
Techniques for configuring multi-path feedback loops Nov 4, 2009 Issued
Array ( [id] => 7796545 [patent_doc_number] => 08125253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'System and method for dynamically switching between low and high frequency reference clock to PLL and minimizing PLL output frequency changes' [patent_app_type] => utility [patent_app_number] => 12/610438 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 16645 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125253.pdf [firstpage_image] =>[orig_patent_app_number] => 12610438 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/610438
System and method for dynamically switching between low and high frequency reference clock to PLL and minimizing PLL output frequency changes Nov 1, 2009 Issued
Array ( [id] => 6522223 [patent_doc_number] => 20100123492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'CONTROL APPARATUS AND CLOCK SYNCHRONIZING METHOD' [patent_app_type] => utility [patent_app_number] => 12/609460 [patent_app_country] => US [patent_app_date] => 2009-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6283 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20100123492.pdf [firstpage_image] =>[orig_patent_app_number] => 12609460 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/609460
CONTROL APPARATUS AND CLOCK SYNCHRONIZING METHOD Oct 29, 2009 Abandoned
Array ( [id] => 5941412 [patent_doc_number] => 20110102032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'LOOP FILTER' [patent_app_type] => utility [patent_app_number] => 12/608788 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4230 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20110102032.pdf [firstpage_image] =>[orig_patent_app_number] => 12608788 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/608788
Loop filter Oct 28, 2009 Issued
Array ( [id] => 5981226 [patent_doc_number] => 20110095794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'Enhancement of Power Management Using Dynamic Voltage and Frequency Scaling and Digital Phase Lock Loop High Speed Bypass Mode' [patent_app_type] => utility [patent_app_number] => 12/607981 [patent_app_country] => US [patent_app_date] => 2009-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7127 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20110095794.pdf [firstpage_image] =>[orig_patent_app_number] => 12607981 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/607981
Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode Oct 27, 2009 Issued
Array ( [id] => 7713920 [patent_doc_number] => 08093933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Method of fast tracking and jitter improvement in asynchronous sample rate conversion' [patent_app_type] => utility [patent_app_number] => 12/606195 [patent_app_country] => US [patent_app_date] => 2009-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6960 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/093/08093933.pdf [firstpage_image] =>[orig_patent_app_number] => 12606195 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/606195
Method of fast tracking and jitter improvement in asynchronous sample rate conversion Oct 26, 2009 Issued
Array ( [id] => 6605871 [patent_doc_number] => 20100033222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'PULSE CONTROL DEVICE' [patent_app_type] => utility [patent_app_number] => 12/579705 [patent_app_country] => US [patent_app_date] => 2009-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3994 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20100033222.pdf [firstpage_image] =>[orig_patent_app_number] => 12579705 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/579705
Pulse control device Oct 14, 2009 Issued
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