Search

Srirama T. Channavajjala

Examiner (ID: 8544)

Most Active Art Unit
2157
Art Unit(s)
2157, 2154, 2164, 2771, 2177, 2158, 2777, 2166, 2161, 2776
Total Applications
1249
Issued Applications
847
Pending Applications
104
Abandoned Applications
304

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19727670 [patent_doc_number] => 20250030421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => CHANNEL BASED CONFIGURABLE CML, LVDS, OPEN DRAIN OUTPUT [patent_app_type] => utility [patent_app_number] => 18/223371 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223371 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223371
Channel based configurable CML, LVDS, open drain output Jul 17, 2023 Issued
Array ( [id] => 19885507 [patent_doc_number] => 12271220 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-08 [patent_title] => Managing multi-phase clock signals for integrated circuit devices [patent_app_type] => utility [patent_app_number] => 18/345725 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345725 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345725
Managing multi-phase clock signals for integrated circuit devices Jun 29, 2023 Issued
Array ( [id] => 19538103 [patent_doc_number] => 12130656 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-29 [patent_title] => Skew-correcting clock buffer [patent_app_type] => utility [patent_app_number] => 18/343841 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343841 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343841
Skew-correcting clock buffer Jun 28, 2023 Issued
Array ( [id] => 19900678 [patent_doc_number] => 12278623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Power on reset (POR) circuit [patent_app_type] => utility [patent_app_number] => 18/332522 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332522 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332522
Power on reset (POR) circuit Jun 8, 2023 Issued
Array ( [id] => 20623345 [patent_doc_number] => 12590848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Temperature sensor and electronic system for executing trimming operations [patent_app_type] => utility [patent_app_number] => 18/330471 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330471 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/330471
Temperature sensor and electronic system for executing trimming operations Jun 6, 2023 Issued
Array ( [id] => 18959805 [patent_doc_number] => 20240048132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => DUAL-EDGE-TRIGGERED FLIP-FLOP [patent_app_type] => utility [patent_app_number] => 18/330731 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330731 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/330731
Dual-edge-triggered flip-flop Jun 6, 2023 Issued
Array ( [id] => 19720982 [patent_doc_number] => 12206532 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-21 [patent_title] => Wireline receiver sampling circuit [patent_app_type] => utility [patent_app_number] => 18/329774 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/329774
Wireline receiver sampling circuit Jun 5, 2023 Issued
Array ( [id] => 19400207 [patent_doc_number] => 12074603 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-08-27 [patent_title] => Leakage-free dummy cell for semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/313384 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6162 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313384 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/313384
Leakage-free dummy cell for semiconductor devices May 7, 2023 Issued
Array ( [id] => 19101699 [patent_doc_number] => 20240120927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => PHASE-LOCKED LOOP DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/142939 [patent_app_country] => US [patent_app_date] => 2023-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18142939 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/142939
Phase-locked loop device and operation method thereof May 2, 2023 Issued
Array ( [id] => 19547312 [patent_doc_number] => 20240364348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SYNCHRONIZATION OF MULTIPLE CLOCK DIVIDERS BY USING LOWER-FREQUENCY CLOCKS AND SLIPPING CYCLES [patent_app_type] => utility [patent_app_number] => 18/308783 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308783 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/308783
Synchronization of multiple clock dividers by using lower-frequency clocks and slipping cycles Apr 27, 2023 Issued
Array ( [id] => 19329384 [patent_doc_number] => 12047079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Flip-flop circuit and method [patent_app_type] => utility [patent_app_number] => 18/302178 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 12477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302178 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/302178
Flip-flop circuit and method Apr 17, 2023 Issued
Array ( [id] => 20118712 [patent_doc_number] => 12368434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => D flip-flop having multiplexer function [patent_app_type] => utility [patent_app_number] => 18/272053 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 33 [patent_no_of_words] => 3642 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 531 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18272053 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/272053
D flip-flop having multiplexer function Apr 11, 2023 Issued
Array ( [id] => 19944191 [patent_doc_number] => 12316334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Method and circuit for DLL locking mechanism for wide range harmonic detection and false lock detection [patent_app_type] => utility [patent_app_number] => 18/194049 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 5146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/194049
Method and circuit for DLL locking mechanism for wide range harmonic detection and false lock detection Mar 30, 2023 Issued
Array ( [id] => 18697212 [patent_doc_number] => 20230327671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => VOLTAGE LEVEL SHIFTER AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/185399 [patent_app_country] => US [patent_app_date] => 2023-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18185399 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/185399
Voltage level shifter and operation method thereof Mar 16, 2023 Issued
Array ( [id] => 18488051 [patent_doc_number] => 20230215397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => Driver Circuit, Display Device, And Electronic Device [patent_app_type] => utility [patent_app_number] => 18/120489 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120489 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/120489
Driver circuit, display device, and electronic device Mar 12, 2023 Issued
Array ( [id] => 19782085 [patent_doc_number] => 12231132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Systems and methods for PLL duty cycle calibration [patent_app_type] => utility [patent_app_number] => 18/120838 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 11566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120838 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/120838
Systems and methods for PLL duty cycle calibration Mar 12, 2023 Issued
Array ( [id] => 19055333 [patent_doc_number] => 20240097302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => DIGITAL ISOLATOR [patent_app_type] => utility [patent_app_number] => 18/118271 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18118271 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/118271
Digital isolator Mar 6, 2023 Issued
Array ( [id] => 19734319 [patent_doc_number] => 12212327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods [patent_app_type] => utility [patent_app_number] => 18/114847 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7908 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18114847 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/114847
Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods Feb 26, 2023 Issued
Array ( [id] => 19393565 [patent_doc_number] => 20240283435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => Scan Flip Flop [patent_app_type] => utility [patent_app_number] => 18/171074 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171074 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171074
Scan Flip Flop Feb 16, 2023 Abandoned
Array ( [id] => 19391175 [patent_doc_number] => 20240281045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => Voltage Droop Monitor [patent_app_type] => utility [patent_app_number] => 18/170864 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170864
Voltage Droop Monitor Feb 16, 2023 Abandoned
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