Search

Srirama T. Channavajjala

Examiner (ID: 8544)

Most Active Art Unit
2157
Art Unit(s)
2157, 2154, 2164, 2771, 2177, 2158, 2777, 2166, 2161, 2776
Total Applications
1249
Issued Applications
847
Pending Applications
104
Abandoned Applications
304

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18805226 [patent_doc_number] => 11838398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/051138 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 15946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051138 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051138
Semiconductor device Oct 30, 2022 Issued
Array ( [id] => 19138516 [patent_doc_number] => 11973497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-30 [patent_title] => Parameterized superconducting multi-row circuit [patent_app_type] => utility [patent_app_number] => 18/050187 [patent_app_country] => US [patent_app_date] => 2022-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18050187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/050187
Parameterized superconducting multi-row circuit Oct 26, 2022 Issued
Array ( [id] => 18464890 [patent_doc_number] => 11689190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => D flip-flop [patent_app_type] => utility [patent_app_number] => 17/973740 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 10009 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 623 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/973740
D flip-flop Oct 25, 2022 Issued
Array ( [id] => 19131663 [patent_doc_number] => 20240137016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => ADAPTIVE CLOCK GATING FOR IMPROVING WEAR OUT-INDUCED DUTY CYCLE SHIFT IN COMPUTER CLOCK NETWORK [patent_app_type] => utility [patent_app_number] => 17/971619 [patent_app_country] => US [patent_app_date] => 2022-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17971619 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/971619
ADAPTIVE CLOCK GATING FOR IMPROVING WEAR OUT-INDUCED DUTY CYCLE SHIFT IN COMPUTER CLOCK NETWORK Oct 22, 2022 Pending
Array ( [id] => 19131663 [patent_doc_number] => 20240137016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => ADAPTIVE CLOCK GATING FOR IMPROVING WEAR OUT-INDUCED DUTY CYCLE SHIFT IN COMPUTER CLOCK NETWORK [patent_app_type] => utility [patent_app_number] => 17/971619 [patent_app_country] => US [patent_app_date] => 2022-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17971619 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/971619
ADAPTIVE CLOCK GATING FOR IMPROVING WEAR OUT-INDUCED DUTY CYCLE SHIFT IN COMPUTER CLOCK NETWORK Oct 21, 2022 Pending
Array ( [id] => 19951781 [patent_doc_number] => 12323156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Clock signal generation circuit [patent_app_type] => utility [patent_app_number] => 17/968791 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17968791 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/968791
Clock signal generation circuit Oct 17, 2022 Issued
Array ( [id] => 18139315 [patent_doc_number] => 20230013151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => CLOCK CIRCUIT IN A PROCESSOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/947699 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17947699 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/947699
Clock circuit in a processor integrated circuit Sep 18, 2022 Issued
Array ( [id] => 18112571 [patent_doc_number] => 20230005451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => Control system with cascade driving circuits and related driving method [patent_app_type] => utility [patent_app_number] => 17/945082 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/945082
Control system with cascade driving circuits and related driving method Sep 13, 2022 Issued
Array ( [id] => 18927913 [patent_doc_number] => 20240030917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS [patent_app_type] => utility [patent_app_number] => 17/932075 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932075
LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS Sep 13, 2022 Pending
Array ( [id] => 19230171 [patent_doc_number] => 12009816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Level-conversion circuits for signaling across voltage domains [patent_app_type] => utility [patent_app_number] => 17/932052 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 35 [patent_no_of_words] => 6247 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932052 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932052
Level-conversion circuits for signaling across voltage domains Sep 13, 2022 Issued
Array ( [id] => 18927914 [patent_doc_number] => 20240030918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS [patent_app_type] => utility [patent_app_number] => 17/932091 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932091 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932091
Level-conversion circuits for signaling across voltage domains Sep 13, 2022 Issued
Array ( [id] => 18640132 [patent_doc_number] => 11764764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-19 [patent_title] => Latch device and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/943225 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943225 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943225
Latch device and operation method thereof Sep 12, 2022 Issued
Array ( [id] => 19039083 [patent_doc_number] => 20240088898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => Timing Controlled Level Shifter Circuit [patent_app_type] => utility [patent_app_number] => 17/931055 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17931055 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/931055
Timing controlled level shifter circuit Sep 8, 2022 Issued
Array ( [id] => 18279458 [patent_doc_number] => 20230094930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => LEVEL SHIFTER CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/901377 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901377 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901377
Level shifter circuit Aug 31, 2022 Issued
Array ( [id] => 18999686 [patent_doc_number] => 11916549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-27 [patent_title] => Two-stage high speed level shifter [patent_app_type] => utility [patent_app_number] => 17/898263 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 15042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898263 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/898263
Two-stage high speed level shifter Aug 28, 2022 Issued
Array ( [id] => 18999693 [patent_doc_number] => 11916556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-27 [patent_title] => Method of operation for a data latch circuit [patent_app_type] => utility [patent_app_number] => 17/896479 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896479 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896479
Method of operation for a data latch circuit Aug 25, 2022 Issued
Array ( [id] => 18555954 [patent_doc_number] => 20230253971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => DELAY LOCKED LOOP INCLUDING REPLICA FINE DELAY CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/888199 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888199 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888199
Delay locked loop including replica fine delay circuit and memory device including the same Aug 14, 2022 Issued
Array ( [id] => 18797465 [patent_doc_number] => 11831310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Level shifting circuit and method [patent_app_type] => utility [patent_app_number] => 17/883257 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 16043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883257
Level shifting circuit and method Aug 7, 2022 Issued
Array ( [id] => 18561299 [patent_doc_number] => 11726542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Power management circuit and method [patent_app_type] => utility [patent_app_number] => 17/883266 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883266 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883266
Power management circuit and method Aug 7, 2022 Issued
Array ( [id] => 18782757 [patent_doc_number] => 11824533 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-21 [patent_title] => Level-conversion circuits utilizing level-dependent inverter supply voltages [patent_app_type] => utility [patent_app_number] => 17/814752 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814752 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814752
Level-conversion circuits utilizing level-dependent inverter supply voltages Jul 24, 2022 Issued
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