Search

Stanetta D. Isaac

Examiner (ID: 13945, Phone: (571)272-1671 , Office: P/2898 )

Most Active Art Unit
2898
Art Unit(s)
2812, 2898
Total Applications
1425
Issued Applications
1158
Pending Applications
132
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17870751 [patent_doc_number] => 20220293488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => HEAT SINK FOR IC COMPONENT AND IC HEAT SINK ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/633921 [patent_app_country] => US [patent_app_date] => 2020-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17633921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/633921
HEAT SINK FOR IC COMPONENT AND IC HEAT SINK ASSEMBLY Aug 6, 2020 Pending
Array ( [id] => 17862905 [patent_doc_number] => 11444066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Display apparatus and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/984216 [patent_app_country] => US [patent_app_date] => 2020-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13663 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/984216
Display apparatus and manufacturing method thereof Aug 3, 2020 Issued
Array ( [id] => 16456121 [patent_doc_number] => 20200365547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => SEMICONDUCTOR APPARATUS WITH HIGH-STABILITY BONDING LAYER AND PRODUCTION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/984805 [patent_app_country] => US [patent_app_date] => 2020-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/984805
SEMICONDUCTOR APPARATUS WITH HIGH-STABILITY BONDING LAYER AND PRODUCTION METHOD THEREOF Aug 3, 2020 Abandoned
Array ( [id] => 17389345 [patent_doc_number] => 20220037197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/941526 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941526 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941526
METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE Jul 27, 2020 Abandoned
Array ( [id] => 17040622 [patent_doc_number] => 20210257258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => Multiple Threshold Voltage Implementation Through Lanthanum Incorporation [patent_app_type] => utility [patent_app_number] => 16/939610 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939610 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939610
Multiple threshold voltage implementation through lanthanum incorporation Jul 26, 2020 Issued
Array ( [id] => 16812114 [patent_doc_number] => 20210134669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => ISOLATION STRUCTURE FOR METAL INTERCONNECT [patent_app_type] => utility [patent_app_number] => 16/939994 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939994 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939994
ISOLATION STRUCTURE FOR METAL INTERCONNECT Jul 26, 2020 Issued
Array ( [id] => 16812114 [patent_doc_number] => 20210134669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => ISOLATION STRUCTURE FOR METAL INTERCONNECT [patent_app_type] => utility [patent_app_number] => 16/939994 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939994 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939994
ISOLATION STRUCTURE FOR METAL INTERCONNECT Jul 26, 2020 Issued
Array ( [id] => 16812114 [patent_doc_number] => 20210134669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => ISOLATION STRUCTURE FOR METAL INTERCONNECT [patent_app_type] => utility [patent_app_number] => 16/939994 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939994 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939994
ISOLATION STRUCTURE FOR METAL INTERCONNECT Jul 26, 2020 Issued
Array ( [id] => 16812114 [patent_doc_number] => 20210134669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => ISOLATION STRUCTURE FOR METAL INTERCONNECT [patent_app_type] => utility [patent_app_number] => 16/939994 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939994 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939994
ISOLATION STRUCTURE FOR METAL INTERCONNECT Jul 26, 2020 Issued
Array ( [id] => 16601588 [patent_doc_number] => 20210028119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => Power Semiconductor Device and Manufacturing Method [patent_app_type] => utility [patent_app_number] => 16/937644 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937644 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937644
Power Semiconductor Device and Manufacturing Method Jul 23, 2020 Pending
Array ( [id] => 16394382 [patent_doc_number] => 20200335323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => SEMICONDUCTOR STRUCTURE WITH PATTERNED FIN STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/921232 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921232 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921232
Semiconductor structure with patterned fin structure Jul 5, 2020 Issued
Array ( [id] => 18473091 [patent_doc_number] => 20230207379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => METHOD AND DEVICE FOR BONDING SUBSTRATES [patent_app_type] => utility [patent_app_number] => 17/928134 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17928134 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/928134
METHOD AND DEVICE FOR BONDING SUBSTRATES Jun 28, 2020 Pending
Array ( [id] => 17318982 [patent_doc_number] => 20210408032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE INCLUDING III-V COMPOUND SEMICONDUCTOR CHANNEL LAYER AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/912196 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912196 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/912196
Three-dimensional memory device including III-V compound semiconductor channel layer and method of making the same Jun 24, 2020 Issued
Array ( [id] => 18319570 [patent_doc_number] => 20230117698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => OLED DISPLAY PANEL AND OLED DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/970960 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16970960 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/970960
OLED display panel and OLED display device Jun 18, 2020 Issued
Array ( [id] => 16348098 [patent_doc_number] => 20200312749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/903706 [patent_app_country] => US [patent_app_date] => 2020-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903706 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/903706
Semiconductor devices and methods of making the same Jun 16, 2020 Issued
Array ( [id] => 17855268 [patent_doc_number] => 20220285311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => Installing an Electronic Assembly [patent_app_type] => utility [patent_app_number] => 17/630030 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17630030 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/630030
Installing an Electronic Assembly Jun 14, 2020 Abandoned
Array ( [id] => 17977681 [patent_doc_number] => 11494543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Layout for integrated circuit and the integrated circuit [patent_app_type] => utility [patent_app_number] => 16/883575 [patent_app_country] => US [patent_app_date] => 2020-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883575 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/883575
Layout for integrated circuit and the integrated circuit May 25, 2020 Issued
Array ( [id] => 17247055 [patent_doc_number] => 20210366800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/877652 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16877652 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/877652
Semiconductor devices and methods of manufacturing semiconductor devices May 18, 2020 Issued
Array ( [id] => 18175089 [patent_doc_number] => 11574806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Film forming method [patent_app_type] => utility [patent_app_number] => 15/930637 [patent_app_country] => US [patent_app_date] => 2020-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 12563 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930637 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/930637
Film forming method May 12, 2020 Issued
Array ( [id] => 17217847 [patent_doc_number] => 20210351185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => SEMICONDUCTOR DEVICE WITH TAPERING IMPURITY REGION AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/867214 [patent_app_country] => US [patent_app_date] => 2020-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16867214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/867214
Semiconductor device with tapering impurity region and method for fabricating the same May 4, 2020 Issued
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