Search

Stanetta D. Isaac

Examiner (ID: 13945, Phone: (571)272-1671 , Office: P/2898 )

Most Active Art Unit
2898
Art Unit(s)
2812, 2898
Total Applications
1425
Issued Applications
1158
Pending Applications
132
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20404398 [patent_doc_number] => 12494378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Method for manufacturing an electronic power module [patent_app_type] => utility [patent_app_number] => 17/609093 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17609093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/609093
Method for manufacturing an electronic power module Apr 23, 2020 Issued
Array ( [id] => 20404398 [patent_doc_number] => 12494378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Method for manufacturing an electronic power module [patent_app_type] => utility [patent_app_number] => 17/609093 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17609093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/609093
Method for manufacturing an electronic power module Apr 23, 2020 Issued
Array ( [id] => 20404398 [patent_doc_number] => 12494378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Method for manufacturing an electronic power module [patent_app_type] => utility [patent_app_number] => 17/609093 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17609093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/609093
Method for manufacturing an electronic power module Apr 23, 2020 Issued
Array ( [id] => 17668560 [patent_doc_number] => 11362265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Semiconductor structure and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/855792 [patent_app_country] => US [patent_app_date] => 2020-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16855792 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/855792
Semiconductor structure and method of manufacturing the same Apr 21, 2020 Issued
Array ( [id] => 16210534 [patent_doc_number] => 20200243524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/845012 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845012 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845012
Semiconductor device Apr 8, 2020 Issued
Array ( [id] => 16981556 [patent_doc_number] => 20210225793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => SILVER NANO-TWINNED THIN FILM STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/844972 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844972 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/844972
Silver nano-twinned thin film structure and method for forming the same Apr 8, 2020 Issued
Array ( [id] => 17254032 [patent_doc_number] => 11189530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Manufacturing method of chips [patent_app_type] => utility [patent_app_number] => 16/842235 [patent_app_country] => US [patent_app_date] => 2020-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 12235 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16842235 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/842235
Manufacturing method of chips Apr 6, 2020 Issued
Array ( [id] => 17253987 [patent_doc_number] => 11189485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Steam oxidation initiation for high aspect ratio conformal radical oxidation [patent_app_type] => utility [patent_app_number] => 16/836351 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836351 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836351
Steam oxidation initiation for high aspect ratio conformal radical oxidation Mar 30, 2020 Issued
Array ( [id] => 16180388 [patent_doc_number] => 20200227357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => Method of Forming Semiconductor Device [patent_app_type] => utility [patent_app_number] => 16/834103 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834103 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834103
Method of forming semiconductor device Mar 29, 2020 Issued
Array ( [id] => 17745710 [patent_doc_number] => 11393792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Semiconductor device with connection structure and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/829665 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 11051 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829665 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/829665
Semiconductor device with connection structure and method for fabricating the same Mar 24, 2020 Issued
Array ( [id] => 16316116 [patent_doc_number] => 20200294854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES [patent_app_type] => utility [patent_app_number] => 16/826651 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826651 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/826651
VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES Mar 22, 2020 Pending
Array ( [id] => 16316116 [patent_doc_number] => 20200294854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES [patent_app_type] => utility [patent_app_number] => 16/826651 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826651 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/826651
VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES Mar 22, 2020 Pending
Array ( [id] => 16731455 [patent_doc_number] => 20210098603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => Stress-Inducing Silicon Liner in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 16/820175 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16820175 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/820175
Stress-inducing silicon liner in semiconductor devices Mar 15, 2020 Issued
Array ( [id] => 16812395 [patent_doc_number] => 20210134950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => TUNING THRESHOLD VOLTAGE IN NANOSHEET TRANSITOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/819632 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16819632 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/819632
Tuning threshold voltage in nanosheet transitor devices Mar 15, 2020 Issued
Array ( [id] => 16316214 [patent_doc_number] => 20200294952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => SHEET FOR SINTERING BONDING, SHEET FOR SINTERING BONDING WITH BASE MATERIAL, AND SEMICONDUCTOR CHIP WITH LAYER OF MATERIAL FOR SINTERING BONDING [patent_app_type] => utility [patent_app_number] => 16/818323 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818323 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/818323
SHEET FOR SINTERING BONDING, SHEET FOR SINTERING BONDING WITH BASE MATERIAL, AND SEMICONDUCTOR CHIP WITH LAYER OF MATERIAL FOR SINTERING BONDING Mar 12, 2020 Abandoned
Array ( [id] => 18156127 [patent_doc_number] => 11569118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Semiconductor manufacturing apparatus and manufacturing method for semiconductor device [patent_app_type] => utility [patent_app_number] => 16/813126 [patent_app_country] => US [patent_app_date] => 2020-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 46 [patent_no_of_words] => 13266 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813126 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/813126
Semiconductor manufacturing apparatus and manufacturing method for semiconductor device Mar 8, 2020 Issued
Array ( [id] => 16731133 [patent_doc_number] => 20210098281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => METHOD OF FORMING SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/812533 [patent_app_country] => US [patent_app_date] => 2020-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16812533 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/812533
Method of forming semiconductor-on-insulator (SOI) substrate Mar 8, 2020 Issued
Array ( [id] => 17085445 [patent_doc_number] => 20210280452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => CREATING AN IMPLANTED LAYER IN A SILICON-ON-INSULATOR (SOI) WAFER THROUGH CRYSTAL ORIENTATION CHANNELING [patent_app_type] => utility [patent_app_number] => 16/809796 [patent_app_country] => US [patent_app_date] => 2020-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809796 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/809796
CREATING AN IMPLANTED LAYER IN A SILICON-ON-INSULATOR (SOI) WAFER THROUGH CRYSTAL ORIENTATION CHANNELING Mar 4, 2020 Abandoned
Array ( [id] => 16677343 [patent_doc_number] => 20210066109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/807648 [patent_app_country] => US [patent_app_date] => 2020-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807648 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/807648
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Mar 2, 2020 Abandoned
Array ( [id] => 19290784 [patent_doc_number] => 12030125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Bonded body and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 17/434492 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6021 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17434492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/434492
Bonded body and method for manufacturing same Mar 1, 2020 Issued
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