
Stanetta D. Isaac
Examiner (ID: 5767, Phone: (571)272-1671 , Office: P/2898 )
| Most Active Art Unit | 2898 |
| Art Unit(s) | 2812, 2898 |
| Total Applications | 1458 |
| Issued Applications | 1176 |
| Pending Applications | 128 |
| Abandoned Applications | 181 |
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|---|---|---|---|
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