Search

Stanetta D. Isaac

Examiner (ID: 5767, Phone: (571)272-1671 , Office: P/2898 )

Most Active Art Unit
2898
Art Unit(s)
2812, 2898
Total Applications
1458
Issued Applications
1176
Pending Applications
128
Abandoned Applications
181

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15170375 [patent_doc_number] => 10490694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Method for manufacturing light emitting element [patent_app_type] => utility [patent_app_number] => 15/941402 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 10111 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941402 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941402
Method for manufacturing light emitting element Mar 29, 2018 Issued
Array ( [id] => 14930805 [patent_doc_number] => 20190301040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => COPPER ELECTRODEPOSITION ON COBALT LINED FEATURES [patent_app_type] => utility [patent_app_number] => 15/941258 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941258 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941258
Copper electrodeposition on cobalt lined features Mar 29, 2018 Issued
Array ( [id] => 16738848 [patent_doc_number] => 10964512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Semiconductor processing chamber multistage mixing apparatus and methods [patent_app_type] => utility [patent_app_number] => 15/942051 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9940 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15942051 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/942051
Semiconductor processing chamber multistage mixing apparatus and methods Mar 29, 2018 Issued
Array ( [id] => 13306507 [patent_doc_number] => 20180204790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/918466 [patent_app_country] => US [patent_app_date] => 2018-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15918466 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/918466
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Mar 11, 2018 Abandoned
Array ( [id] => 16617510 [patent_doc_number] => 20210036163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => THIN FILM TRANSISTOR AND PRODUCTION METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 16/968045 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16968045 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/968045
THIN FILM TRANSISTOR AND PRODUCTION METHOD THEREFOR Mar 8, 2018 Abandoned
Array ( [id] => 14676709 [patent_doc_number] => 20190237469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => RESISTOR FOR DYNAMIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 15/904428 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904428 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/904428
Resistor for dynamic random access memory Feb 25, 2018 Issued
Array ( [id] => 14631199 [patent_doc_number] => 20190228968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => SOLID PHASE CRYSTALLIZATION METHOD AND MANUFACTURING METHOD OF LOW-TEMPERATURE POLY-SILICON TFT SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/773690 [patent_app_country] => US [patent_app_date] => 2018-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15773690 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/773690
Solid phase crystallization method and manufacturing method of low-temperature poly-silicon TFT substrate Feb 21, 2018 Issued
Array ( [id] => 12850201 [patent_doc_number] => 20180175240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => CONTROLLING OXYGEN CONCENTRATION LEVELS DURING PROCESSING OF HIGHLY-REFLECTIVE CONTACTS [patent_app_type] => utility [patent_app_number] => 15/883174 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15883174 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/883174
Controlling oxygen concentration levels during processing of highly-reflective contacts Jan 29, 2018 Issued
Array ( [id] => 14644495 [patent_doc_number] => 10366997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Semiconductor devices and methods for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/821230 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 12997 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15821230 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/821230
Semiconductor devices and methods for manufacturing the same Nov 21, 2017 Issued
Array ( [id] => 12236247 [patent_doc_number] => 20180069110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/812862 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 12364 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812862 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/812862
Semiconductor device and method of manufacturing the same Nov 13, 2017 Issued
Array ( [id] => 13847823 [patent_doc_number] => 20190027396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => Techniques and Structure for Forming Thin Silicon-on-Insulator Materials [patent_app_type] => utility [patent_app_number] => 15/728000 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728000 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728000
Techniques and structure for forming thin silicon-on-insulator materials Oct 8, 2017 Issued
Array ( [id] => 12188708 [patent_doc_number] => 20180047644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'METHOD AND STRUCTURE FOR FLIP-CHIP PACKAGE RELIABILITY MONITORING USING CAPACITIVE SENSORS GROUPS' [patent_app_type] => utility [patent_app_number] => 15/722459 [patent_app_country] => US [patent_app_date] => 2017-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722459 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/722459
Method and structure for flip-chip package reliability monitoring using capacitive sensors groups Oct 1, 2017 Issued
Array ( [id] => 12141089 [patent_doc_number] => 20180019172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'METHOD AND STRUCTURE FOR FLIP-CHIP PACKAGE RELIABILITY MONITORING USING CAPACITIVE SENSORS GROUPS' [patent_app_type] => utility [patent_app_number] => 15/722547 [patent_app_country] => US [patent_app_date] => 2017-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6052 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722547 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/722547
Method and structure for flip-chip package reliability monitoring using capacitive sensors groups Oct 1, 2017 Issued
Array ( [id] => 20531949 [patent_doc_number] => 12550401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Doped STI to reduce source/drain diffusion for germanium NMOS transistors [patent_app_type] => utility [patent_app_number] => 16/641030 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 8266 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16641030 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/641030
Doped STI to reduce source/drain diffusion for germanium NMOS transistors Sep 28, 2017 Issued
Array ( [id] => 15217699 [patent_doc_number] => 20190371536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => Flexible Supercapacitors and Manufacture Thereof [patent_app_type] => utility [patent_app_number] => 16/334078 [patent_app_country] => US [patent_app_date] => 2017-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16334078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/334078
Flexible Supercapacitors and Manufacture Thereof Sep 20, 2017 Abandoned
Array ( [id] => 13724011 [patent_doc_number] => 20170372961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES [patent_app_type] => utility [patent_app_number] => 15/687636 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687636 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687636
Vias and conductive routing layers in semiconductor substrates Aug 27, 2017 Issued
Array ( [id] => 14011697 [patent_doc_number] => 10224324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Method for manufacturing semiconductor device having gate structure with reduced threshold voltage [patent_app_type] => utility [patent_app_number] => 15/681570 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4209 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681570 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/681570
Method for manufacturing semiconductor device having gate structure with reduced threshold voltage Aug 20, 2017 Issued
Array ( [id] => 12188922 [patent_doc_number] => 20180047858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/671430 [patent_app_country] => US [patent_app_date] => 2017-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4390 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15671430 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/671430
Method of manufacturing a semiconductor device Aug 7, 2017 Issued
Array ( [id] => 15316081 [patent_doc_number] => 10522758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Ink for forming functional layer, method of manufacturing ink for forming functional layer, and method of manufacturing organic electro-luminescence element [patent_app_type] => utility [patent_app_number] => 15/665464 [patent_app_country] => US [patent_app_date] => 2017-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 13846 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15665464 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/665464
Ink for forming functional layer, method of manufacturing ink for forming functional layer, and method of manufacturing organic electro-luminescence element Jul 31, 2017 Issued
Array ( [id] => 12263968 [patent_doc_number] => 20180083163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/658195 [patent_app_country] => US [patent_app_date] => 2017-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5607 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15658195 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/658195
LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME Jul 23, 2017 Abandoned
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