Search

Stanetta D. Isaac

Examiner (ID: 5767, Phone: (571)272-1671 , Office: P/2898 )

Most Active Art Unit
2898
Art Unit(s)
2812, 2898
Total Applications
1458
Issued Applications
1176
Pending Applications
128
Abandoned Applications
181

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18848932 [patent_doc_number] => 20230411336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => SEMICONDUCTOR WAFER, CLIP AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/364483 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364483 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364483
SEMICONDUCTOR WAFER, CLIP AND SEMICONDUCTOR DEVICE Aug 2, 2023 Pending
Array ( [id] => 19758086 [patent_doc_number] => 20250046651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => OPTIMAL HIGH VOLTAGE TUB DESIGN WITH FLOATING POLY TRENCHES [patent_app_type] => utility [patent_app_number] => 18/228934 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228934 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228934
OPTIMAL HIGH VOLTAGE TUB DESIGN WITH FLOATING POLY TRENCHES Jul 31, 2023 Pending
Array ( [id] => 18907975 [patent_doc_number] => 20240023460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/360510 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360510 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360510
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME Jul 26, 2023 Pending
Array ( [id] => 18943572 [patent_doc_number] => 20240038711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/359976 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359976 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359976
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE Jul 26, 2023 Pending
Array ( [id] => 18906116 [patent_doc_number] => 20240021601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => BCD DEVICE LAYOUT AREA DEFINED BY A DEEP TRENCH ISOLATION STRUCTURE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/358167 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358167 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358167
BCD device layout area defined by a deep trench isolation structure and methods for forming the same Jul 24, 2023 Issued
Array ( [id] => 18743424 [patent_doc_number] => 20230352412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => MULTIPLE DIE PACKAGE USING AN EMBEDDED BRIDGE CONNECTING DIES [patent_app_type] => utility [patent_app_number] => 18/221184 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221184 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221184
Multiple die package using an embedded bridge connecting dies Jul 11, 2023 Issued
Array ( [id] => 18743351 [patent_doc_number] => 20230352339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 18/344565 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344565 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344565
Semiconductor devices and methods of manufacturing thereof Jun 28, 2023 Issued
Array ( [id] => 18714720 [patent_doc_number] => 20230337364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => PRINTED CIRCUIT FILM, DISPLAY DEVICE, AND METHOD OF FABRICATING PRINTED CIRCUIT FILM [patent_app_type] => utility [patent_app_number] => 18/212719 [patent_app_country] => US [patent_app_date] => 2023-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212719 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/212719
Printed circuit film, display device, and method of fabricating printed circuit film Jun 21, 2023 Issued
Array ( [id] => 19781668 [patent_doc_number] => 12230707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Source contact formation of MOSFET with gate shield buffer for pitch reduction [patent_app_type] => utility [patent_app_number] => 18/338572 [patent_app_country] => US [patent_app_date] => 2023-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4256 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 526 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338572 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/338572
Source contact formation of MOSFET with gate shield buffer for pitch reduction Jun 20, 2023 Issued
Array ( [id] => 19223616 [patent_doc_number] => 20240188320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => ORGANIC ELECTROLUMINESCENT DEVICES [patent_app_type] => utility [patent_app_number] => 18/206778 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206778
ORGANIC ELECTROLUMINESCENT DEVICES Jun 6, 2023 Pending
Array ( [id] => 18679921 [patent_doc_number] => 20230317579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SEMICONDUCTOR PACKAGE WITH GUIDE PIN [patent_app_type] => utility [patent_app_number] => 18/329203 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329203 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/329203
Semiconductor package with guide pin Jun 4, 2023 Issued
Array ( [id] => 18653054 [patent_doc_number] => 20230298894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => COPPER ELECTRODEPOSITION SEQUENCE FOR THE FILLING OF COBALT LINED FEATURES [patent_app_type] => utility [patent_app_number] => 18/202062 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202062 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202062
COPPER ELECTRODEPOSITION SEQUENCE FOR THE FILLING OF COBALT LINED FEATURES May 24, 2023 Pending
Array ( [id] => 18615814 [patent_doc_number] => 20230282553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => POWER ELECTRONIC ASSEMBLY AND POWER MODULE FOR EMBEDDING IN A PRINTED CIRCUIT BOARD [patent_app_type] => utility [patent_app_number] => 18/315787 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315787 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315787
POWER ELECTRONIC ASSEMBLY AND POWER MODULE FOR EMBEDDING IN A PRINTED CIRCUIT BOARD May 10, 2023 Pending
Array ( [id] => 18615873 [patent_doc_number] => 20230282612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => MECHANICAL WAFER ALIGNMENT DETECTION FOR BONDING PROCESS [patent_app_type] => utility [patent_app_number] => 18/313492 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313492 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/313492
Mechanical wafer alignment detection for bonding process May 7, 2023 Issued
Array ( [id] => 18600296 [patent_doc_number] => 20230275097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => SEMICONDUCTOR-ON-INSULATOR WAFER HAVING A COMPOSITE INSULATOR LAYER [patent_app_type] => utility [patent_app_number] => 18/309905 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309905 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309905
Semiconductor-on-insulator wafer having a composite insulator layer Apr 30, 2023 Issued
Array ( [id] => 19900237 [patent_doc_number] => 12278174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Power semiconductor device with a double island surface mount package [patent_app_type] => utility [patent_app_number] => 18/306119 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306119 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306119
Power semiconductor device with a double island surface mount package Apr 23, 2023 Issued
Array ( [id] => 20625971 [patent_doc_number] => 12593496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Multiple threshold voltage implementation through lanthanum incorporation [patent_app_type] => utility [patent_app_number] => 18/303173 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 4170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303173 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/303173
Multiple threshold voltage implementation through lanthanum incorporation Apr 18, 2023 Issued
Array ( [id] => 18555482 [patent_doc_number] => 20230253499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => DIFFUSED TIP EXTENSION TRANSISTOR [patent_app_type] => utility [patent_app_number] => 18/134418 [patent_app_country] => US [patent_app_date] => 2023-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134418 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134418
DIFFUSED TIP EXTENSION TRANSISTOR Apr 12, 2023 Abandoned
Array ( [id] => 18540826 [patent_doc_number] => 20230245937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/133291 [patent_app_country] => US [patent_app_date] => 2023-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18133291 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/133291
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES Apr 10, 2023 Pending
Array ( [id] => 19191521 [patent_doc_number] => 20240170434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => BACK SIDE METALLIZATION THIN FILM STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/193012 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193012 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/193012
BACK SIDE METALLIZATION THIN FILM STRUCTURE AND METHOD FOR FORMING THE SAME Mar 29, 2023 Pending
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