
Stanetta D. Isaac
Examiner (ID: 5767, Phone: (571)272-1671 , Office: P/2898 )
| Most Active Art Unit | 2898 |
| Art Unit(s) | 2812, 2898 |
| Total Applications | 1458 |
| Issued Applications | 1176 |
| Pending Applications | 128 |
| Abandoned Applications | 181 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18363249
[patent_doc_number] => 20230144840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-11
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/894572
[patent_app_country] => US
[patent_app_date] => 2022-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9450
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 299
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894572
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/894572 | Semiconductor device | Aug 23, 2022 | Issued |
Array
(
[id] => 18757564
[patent_doc_number] => 20230361027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-09
[patent_title] => Semiconductor Device and Method of Manufacture
[patent_app_type] => utility
[patent_app_number] => 17/819381
[patent_app_country] => US
[patent_app_date] => 2022-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9025
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819381
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/819381 | Semiconductor Device and Method of Manufacture | Aug 11, 2022 | Pending |
Array
(
[id] => 20318110
[patent_doc_number] => 12456665
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-28
[patent_title] => Resin-sealed semiconductor device and method for manufacturing resin-sealed semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/886002
[patent_app_country] => US
[patent_app_date] => 2022-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 0
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886002
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/886002 | Resin-sealed semiconductor device and method for manufacturing resin-sealed semiconductor device | Aug 10, 2022 | Issued |
Array
(
[id] => 19605091
[patent_doc_number] => 20240395971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-28
[patent_title] => OPTOELECTRONIC COMPONENT, COMPONENT UNIT AND METHOD FOR PRODUCING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/689715
[patent_app_country] => US
[patent_app_date] => 2022-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7483
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18689715
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/689715 | OPTOELECTRONIC COMPONENT, COMPONENT UNIT AND METHOD FOR PRODUCING THE SAME | Aug 9, 2022 | Pending |
Array
(
[id] => 18229892
[patent_doc_number] => 20230068886
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => PACKAGED SEMICONDUCTOR DEVICE, LEADFRAME AND METHOD FOR IMPROVED BONDING
[patent_app_type] => utility
[patent_app_number] => 17/818778
[patent_app_country] => US
[patent_app_date] => 2022-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3781
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818778
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/818778 | PACKAGED SEMICONDUCTOR DEVICE, LEADFRAME AND METHOD FOR IMPROVED BONDING | Aug 9, 2022 | Issued |
Array
(
[id] => 18038732
[patent_doc_number] => 20220382948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => LAYOUT FOR INTEGRATED CIRCUIT AND THE INTEGRATED CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 17/818417
[patent_app_country] => US
[patent_app_date] => 2022-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9040
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818417
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/818417 | Layout for integrated circuit and the integrated circuit | Aug 8, 2022 | Issued |
Array
(
[id] => 20229288
[patent_doc_number] => 12417944
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-16
[patent_title] => Formation of trench silicide source or drain contacts without gate damage
[patent_app_type] => utility
[patent_app_number] => 17/817365
[patent_app_country] => US
[patent_app_date] => 2022-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 29
[patent_no_of_words] => 1123
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17817365
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/817365 | Formation of trench silicide source or drain contacts without gate damage | Aug 3, 2022 | Issued |
Array
(
[id] => 19604667
[patent_doc_number] => 20240395547
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-28
[patent_title] => SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/689669
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7888
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18689669
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/689669 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS | Jul 25, 2022 | Pending |
Array
(
[id] => 18008910
[patent_doc_number] => 20220367677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => STRESS-INDUCING SILICON LINER IN SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/815181
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7660
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815181
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/815181 | Stress-inducing silicon liner in semiconductor devices | Jul 25, 2022 | Issued |
Array
(
[id] => 18008467
[patent_doc_number] => 20220367234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => DICING DIE ATTACH FILM AND METHOD OF PRODUCING THE SAME, AND SEMICONDUCTOR PACKAGE AND METHOD OF PRODUCING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/872568
[patent_app_country] => US
[patent_app_date] => 2022-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15140
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872568
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/872568 | DICING DIE ATTACH FILM AND METHOD OF PRODUCING THE SAME, AND SEMICONDUCTOR PACKAGE AND METHOD OF PRODUCING THE SAME | Jul 24, 2022 | Pending |
Array
(
[id] => 20675504
[patent_doc_number] => 12616039
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-28
[patent_title] => Electronic system having intermetallic connection structure with central intermetallic mesh structure and mesh-free exterior structures
[patent_app_type] => utility
[patent_app_number] => 17/872338
[patent_app_country] => US
[patent_app_date] => 2022-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 18
[patent_no_of_words] => 6215
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872338
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/872338 | Electronic system having intermetallic connection structure with central intermetallic mesh structure and mesh-free exterior structures | Jul 24, 2022 | Issued |
Array
(
[id] => 19221593
[patent_doc_number] => 20240186297
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => LIGHT-EMITTING PANEL, METHOD FOR FABRICATING SAME, AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/795524
[patent_app_country] => US
[patent_app_date] => 2022-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9557
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17795524
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/795524 | Light-emitting panel, method for fabricating same, and display device | Jul 24, 2022 | Issued |
Array
(
[id] => 18927164
[patent_doc_number] => 20240030168
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => WAFER-ON-WAFER PACKAGING WITH CONTINUOUS SEAL RING
[patent_app_type] => utility
[patent_app_number] => 17/814525
[patent_app_country] => US
[patent_app_date] => 2022-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10570
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814525
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/814525 | WAFER-ON-WAFER PACKAGING WITH CONTINUOUS SEAL RING | Jul 23, 2022 | Pending |
Array
(
[id] => 20161344
[patent_doc_number] => 12387979
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-12
[patent_title] => Tungsten feature fill with nucleation inhibition
[patent_app_type] => utility
[patent_app_number] => 17/814297
[patent_app_country] => US
[patent_app_date] => 2022-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 25
[patent_no_of_words] => 6297
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814297
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/814297 | Tungsten feature fill with nucleation inhibition | Jul 21, 2022 | Issued |
Array
(
[id] => 20443107
[patent_doc_number] => 12513953
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-30
[patent_title] => Tuning threshold voltage in nanosheet transitor devices
[patent_app_type] => utility
[patent_app_number] => 17/868831
[patent_app_country] => US
[patent_app_date] => 2022-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 32
[patent_no_of_words] => 10385
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868831
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/868831 | Tuning threshold voltage in nanosheet transitor devices | Jul 19, 2022 | Issued |
Array
(
[id] => 17949246
[patent_doc_number] => 20220336265
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => METHOD OF FORMING SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 17/854750
[patent_app_country] => US
[patent_app_date] => 2022-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11147
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854750
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/854750 | METHOD OF FORMING SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE | Jun 29, 2022 | Pending |
Array
(
[id] => 18883160
[patent_doc_number] => 20240006529
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-04
[patent_title] => LATERALLY-DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICES WITH A FIELD PLATE
[patent_app_type] => utility
[patent_app_number] => 17/852514
[patent_app_country] => US
[patent_app_date] => 2022-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4034
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852514
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/852514 | LATERALLY-DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICES WITH A FIELD PLATE | Jun 28, 2022 | Pending |
Array
(
[id] => 18181065
[patent_doc_number] => 20230041794
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-09
[patent_title] => TUNGSTEN FEATURE FILL WITH NUCLEATION INHIBITION
[patent_app_type] => utility
[patent_app_number] => 17/809480
[patent_app_country] => US
[patent_app_date] => 2022-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8986
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809480
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/809480 | Tungsten feature fill with nucleation inhibition | Jun 27, 2022 | Issued |
Array
(
[id] => 18334846
[patent_doc_number] => 20230126794
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-27
[patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
[patent_app_type] => utility
[patent_app_number] => 17/807847
[patent_app_country] => US
[patent_app_date] => 2022-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9043
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807847
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/807847 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME | Jun 19, 2022 | Abandoned |
Array
(
[id] => 20189784
[patent_doc_number] => 12400908
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-26
[patent_title] => Epitaxial growth method for FDSOI hybrid region
[patent_app_type] => utility
[patent_app_number] => 17/836180
[patent_app_country] => US
[patent_app_date] => 2022-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 0
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 409
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17836180
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/836180 | Epitaxial growth method for FDSOI hybrid region | Jun 8, 2022 | Issued |