Search

Stanetta D. Isaac

Examiner (ID: 8788, Phone: (571)272-1671 , Office: P/2898 )

Most Active Art Unit
2898
Art Unit(s)
2812, 2898
Total Applications
1426
Issued Applications
1162
Pending Applications
125
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17582909 [patent_doc_number] => 20220139764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => ISOLATION STRUCTUE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/499853 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499853
Isolation structure and manufacturing method thereof Oct 11, 2021 Issued
Array ( [id] => 18874775 [patent_doc_number] => 11862598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/495372 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 14828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495372 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495372
Semiconductor device Oct 5, 2021 Issued
Array ( [id] => 17523126 [patent_doc_number] => 20220108975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => SILVER NANOPARTICLES SYNTHESIS METHOD FOR LOW TEMPERATURE AND PRESSURE SINTERING [patent_app_type] => utility [patent_app_number] => 17/492356 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/492356
SILVER NANOPARTICLES SYNTHESIS METHOD FOR LOW TEMPERATURE AND PRESSURE SINTERING Sep 30, 2021 Issued
Array ( [id] => 18285439 [patent_doc_number] => 20230100911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => PARTIAL DICING PROCESS FOR WAFER-LEVEL PACKAGING [patent_app_type] => utility [patent_app_number] => 17/488586 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488586 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488586
PARTIAL DICING PROCESS FOR WAFER-LEVEL PACKAGING Sep 28, 2021 Pending
Array ( [id] => 18624007 [patent_doc_number] => 11757065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Light-emitting component [patent_app_type] => utility [patent_app_number] => 17/487783 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 6048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487783 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/487783
Light-emitting component Sep 27, 2021 Issued
Array ( [id] => 17536618 [patent_doc_number] => 20220115227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR STRUCTURE PREPARATION PROCESS AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/487779 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3769 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/487779
SEMICONDUCTOR STRUCTURE PREPARATION PROCESS AND SEMICONDUCTOR STRUCTURE Sep 27, 2021 Abandoned
Array ( [id] => 18287389 [patent_doc_number] => 20230102861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => A LOW-COST METHOD OF MAKING A HARD MASK FOR HIGH RESOLUTION AND LOW DIMENSIONAL VARIATIONS FOR THE FABRICATION AND MANUFACTURING OF MICRO- AND NANO-DEVICES AND - SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/485993 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485993
Low-cost method of making a hard mask for high resolution and low dimensional variations for the fabrication and manufacturing of micro- and nano-devices and -systems Sep 26, 2021 Issued
Array ( [id] => 18343439 [patent_doc_number] => 11640923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Method for manufacturing FDSOI [patent_app_type] => utility [patent_app_number] => 17/485189 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1951 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485189
Method for manufacturing FDSOI Sep 23, 2021 Issued
Array ( [id] => 17986105 [patent_doc_number] => 20220352142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => BCD DEVICE LAYOUT AREA DEFINED BY A DEEP TRENCH ISOLATION STRUCTURE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/480434 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480434
BCD device layout area defined by a deep trench isolation structure and methods for forming the same Sep 20, 2021 Issued
Array ( [id] => 17917650 [patent_doc_number] => 20220320046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR DIES HAVING DIFFERENT LATTICE DIRECTIONS AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/477629 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477629 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477629
SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR DIES HAVING DIFFERENT LATTICE DIRECTIONS AND METHOD OF FORMING THE SAME Sep 16, 2021 Issued
Array ( [id] => 17949388 [patent_doc_number] => 20220336407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => DIE BONDING STRUCTURES AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/473964 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473964
DIE BONDING STRUCTURES AND METHOD FOR FORMING THE SAME Sep 12, 2021 Abandoned
Array ( [id] => 18782219 [patent_doc_number] => 11823985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Leadframe, semiconductor device, and method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 17/470078 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4749 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470078 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470078
Leadframe, semiconductor device, and method for manufacturing semiconductor device Sep 8, 2021 Issued
Array ( [id] => 17303317 [patent_doc_number] => 20210399156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => HIGH SENSITIVITY SEMICONDUCTOR DEVICE FOR DETECTING FLUID CHEMICAL SPECIES AND RELATED MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/464299 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464299
High sensitivity semiconductor device for detecting fluid chemical species and related manufacturing method Aug 31, 2021 Issued
Array ( [id] => 17463711 [patent_doc_number] => 20220077017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/463131 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463131
Semiconductor module and semiconductor module manufacturing method Aug 30, 2021 Issued
Array ( [id] => 17855138 [patent_doc_number] => 20220285181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SEMICONDUCTOR MANUFACTURING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/460971 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460971 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460971
Semiconductor manufacturing apparatus, and method of manufacturing semiconductor device Aug 29, 2021 Issued
Array ( [id] => 18224394 [patent_doc_number] => 20230063388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 17/458751 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458751
SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING Aug 26, 2021 Pending
Array ( [id] => 18464421 [patent_doc_number] => 11688717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Mechanical wafer alignment detection for bonding process [patent_app_type] => utility [patent_app_number] => 17/412596 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 10447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412596
Mechanical wafer alignment detection for bonding process Aug 25, 2021 Issued
Array ( [id] => 17448283 [patent_doc_number] => 20220068788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => METHOD OF PRODUCING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/412007 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412007
Method of producing semiconductor devices and corresponding semiconductor device Aug 24, 2021 Issued
Array ( [id] => 17599336 [patent_doc_number] => 20220148910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/407576 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407576 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407576
Semiconductor storage device Aug 19, 2021 Issued
Array ( [id] => 17258721 [patent_doc_number] => 20210371706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => METHOD OF PRODUCING ANISOTROPIC CONDUCTIVE FILM AND ANISOTROPIC CONDUCTIVE FILM [patent_app_type] => utility [patent_app_number] => 17/403072 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403072 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403072
Method of producing anisotropic conductive film and anisotropic conductive film Aug 15, 2021 Issued
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