
Stanetta D. Isaac
Examiner (ID: 13945, Phone: (571)272-1671 , Office: P/2898 )
| Most Active Art Unit | 2898 |
| Art Unit(s) | 2812, 2898 |
| Total Applications | 1425 |
| Issued Applications | 1158 |
| Pending Applications | 132 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17870816
[patent_doc_number] => 20220293553
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-15
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/537788
[patent_app_country] => US
[patent_app_date] => 2021-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9806
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -37
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537788
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/537788 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | Nov 29, 2021 | Pending |
Array
(
[id] => 17764758
[patent_doc_number] => 20220238371
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/533000
[patent_app_country] => US
[patent_app_date] => 2021-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7194
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17533000
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/533000 | Semiconductor devices and methods of manufacturing thereof | Nov 21, 2021 | Issued |
Array
(
[id] => 18359207
[patent_doc_number] => 11647626
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-09
[patent_title] => Method for fabricating semiconductor device with tapering impurity region
[patent_app_type] => utility
[patent_app_number] => 17/529514
[patent_app_country] => US
[patent_app_date] => 2021-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 7756
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529514
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529514 | Method for fabricating semiconductor device with tapering impurity region | Nov 17, 2021 | Issued |
Array
(
[id] => 17676652
[patent_doc_number] => 20220189819
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-16
[patent_title] => METHOD FOR MANUFACTURING LOGIC DEVICE ISOLATION IN EMBEDDED STORAGE PROCESS
[patent_app_type] => utility
[patent_app_number] => 17/529871
[patent_app_country] => US
[patent_app_date] => 2021-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1569
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529871
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529871 | Method for manufacturing logic device isolation in embedded storage process | Nov 17, 2021 | Issued |
Array
(
[id] => 17463812
[patent_doc_number] => 20220077118
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => SEMICONDUCTOR DEVICE WITH CONNECTION STRUCTURE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/529496
[patent_app_country] => US
[patent_app_date] => 2021-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11081
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529496
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529496 | Semiconductor device with connection structure and method for fabricating the same | Nov 17, 2021 | Issued |
Array
(
[id] => 18338705
[patent_doc_number] => 20230130654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-27
[patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/521881
[patent_app_country] => US
[patent_app_date] => 2021-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4291
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521881
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/521881 | Manufacturing method of semiconductor device | Nov 8, 2021 | Issued |
Array
(
[id] => 17431893
[patent_doc_number] => 20220059602
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-24
[patent_title] => SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/517406
[patent_app_country] => US
[patent_app_date] => 2021-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5155
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517406
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/517406 | Solid-state imaging device and electronic device | Nov 1, 2021 | Issued |
Array
(
[id] => 19079415
[patent_doc_number] => 11948791
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-02
[patent_title] => Steam oxidation initiation for high aspect ratio conformal radical oxidation
[patent_app_type] => utility
[patent_app_number] => 17/513400
[patent_app_country] => US
[patent_app_date] => 2021-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6141
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17513400
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/513400 | Steam oxidation initiation for high aspect ratio conformal radical oxidation | Oct 27, 2021 | Issued |
Array
(
[id] => 17582909
[patent_doc_number] => 20220139764
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => ISOLATION STRUCTUE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/499853
[patent_app_country] => US
[patent_app_date] => 2021-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5906
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499853
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/499853 | Isolation structure and manufacturing method thereof | Oct 11, 2021 | Issued |
Array
(
[id] => 18874775
[patent_doc_number] => 11862598
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-02
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/495372
[patent_app_country] => US
[patent_app_date] => 2021-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 26
[patent_no_of_words] => 14828
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495372
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/495372 | Semiconductor device | Oct 5, 2021 | Issued |
Array
(
[id] => 17523126
[patent_doc_number] => 20220108975
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-07
[patent_title] => SILVER NANOPARTICLES SYNTHESIS METHOD FOR LOW TEMPERATURE AND PRESSURE SINTERING
[patent_app_type] => utility
[patent_app_number] => 17/492356
[patent_app_country] => US
[patent_app_date] => 2021-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3801
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492356
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/492356 | SILVER NANOPARTICLES SYNTHESIS METHOD FOR LOW TEMPERATURE AND PRESSURE SINTERING | Sep 30, 2021 | Pending |
Array
(
[id] => 18285439
[patent_doc_number] => 20230100911
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => PARTIAL DICING PROCESS FOR WAFER-LEVEL PACKAGING
[patent_app_type] => utility
[patent_app_number] => 17/488586
[patent_app_country] => US
[patent_app_date] => 2021-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2678
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488586
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/488586 | PARTIAL DICING PROCESS FOR WAFER-LEVEL PACKAGING | Sep 28, 2021 | Pending |
Array
(
[id] => 18624007
[patent_doc_number] => 11757065
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-12
[patent_title] => Light-emitting component
[patent_app_type] => utility
[patent_app_number] => 17/487783
[patent_app_country] => US
[patent_app_date] => 2021-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 6048
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487783
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/487783 | Light-emitting component | Sep 27, 2021 | Issued |
Array
(
[id] => 17536618
[patent_doc_number] => 20220115227
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => SEMICONDUCTOR STRUCTURE PREPARATION PROCESS AND SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/487779
[patent_app_country] => US
[patent_app_date] => 2021-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3769
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487779
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/487779 | SEMICONDUCTOR STRUCTURE PREPARATION PROCESS AND SEMICONDUCTOR STRUCTURE | Sep 27, 2021 | Abandoned |
Array
(
[id] => 17536618
[patent_doc_number] => 20220115227
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => SEMICONDUCTOR STRUCTURE PREPARATION PROCESS AND SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/487779
[patent_app_country] => US
[patent_app_date] => 2021-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3769
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487779
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/487779 | SEMICONDUCTOR STRUCTURE PREPARATION PROCESS AND SEMICONDUCTOR STRUCTURE | Sep 27, 2021 | Abandoned |
Array
(
[id] => 18287389
[patent_doc_number] => 20230102861
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => A LOW-COST METHOD OF MAKING A HARD MASK FOR HIGH RESOLUTION AND LOW DIMENSIONAL VARIATIONS FOR THE FABRICATION AND MANUFACTURING OF MICRO- AND NANO-DEVICES AND - SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 17/485993
[patent_app_country] => US
[patent_app_date] => 2021-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6038
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485993
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/485993 | Low-cost method of making a hard mask for high resolution and low dimensional variations for the fabrication and manufacturing of micro- and nano-devices and -systems | Sep 26, 2021 | Issued |
Array
(
[id] => 18343439
[patent_doc_number] => 11640923
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-02
[patent_title] => Method for manufacturing FDSOI
[patent_app_type] => utility
[patent_app_number] => 17/485189
[patent_app_country] => US
[patent_app_date] => 2021-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1951
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485189
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/485189 | Method for manufacturing FDSOI | Sep 23, 2021 | Issued |
Array
(
[id] => 17986105
[patent_doc_number] => 20220352142
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => BCD DEVICE LAYOUT AREA DEFINED BY A DEEP TRENCH ISOLATION STRUCTURE AND METHODS FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/480434
[patent_app_country] => US
[patent_app_date] => 2021-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14393
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480434
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/480434 | BCD device layout area defined by a deep trench isolation structure and methods for forming the same | Sep 20, 2021 | Issued |
Array
(
[id] => 17917650
[patent_doc_number] => 20220320046
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR DIES HAVING DIFFERENT LATTICE DIRECTIONS AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/477629
[patent_app_country] => US
[patent_app_date] => 2021-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12819
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477629
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/477629 | SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR DIES HAVING DIFFERENT LATTICE DIRECTIONS AND METHOD OF FORMING THE SAME | Sep 16, 2021 | Pending |
Array
(
[id] => 17949388
[patent_doc_number] => 20220336407
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => DIE BONDING STRUCTURES AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/473964
[patent_app_country] => US
[patent_app_date] => 2021-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6430
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473964
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/473964 | DIE BONDING STRUCTURES AND METHOD FOR FORMING THE SAME | Sep 12, 2021 | Abandoned |