
Stanetta D. Isaac
Examiner (ID: 8788, Phone: (571)272-1671 , Office: P/2898 )
| Most Active Art Unit | 2898 |
| Art Unit(s) | 2812, 2898 |
| Total Applications | 1426 |
| Issued Applications | 1162 |
| Pending Applications | 125 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20244163
[patent_doc_number] => 12424494
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-23
[patent_title] => Processing method of wafer
[patent_app_type] => utility
[patent_app_number] => 17/330590
[patent_app_country] => US
[patent_app_date] => 2021-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 2367
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330590
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/330590 | Processing method of wafer | May 25, 2021 | Issued |
Array
(
[id] => 19982007
[patent_doc_number] => 12349510
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-01
[patent_title] => Light-emitting diode, light-emitting diode packaged module and display device including the same
[patent_app_type] => utility
[patent_app_number] => 17/303153
[patent_app_country] => US
[patent_app_date] => 2021-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17303153
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/303153 | Light-emitting diode, light-emitting diode packaged module and display device including the same | May 20, 2021 | Issued |
Array
(
[id] => 18935422
[patent_doc_number] => 11887864
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-30
[patent_title] => Method of forming a surface-mount integrated circuit package with solder enhanced leadframe terminals
[patent_app_type] => utility
[patent_app_number] => 17/326488
[patent_app_country] => US
[patent_app_date] => 2021-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 20
[patent_no_of_words] => 5981
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 413
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326488
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/326488 | Method of forming a surface-mount integrated circuit package with solder enhanced leadframe terminals | May 20, 2021 | Issued |
Array
(
[id] => 17070625
[patent_doc_number] => 20210272842
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-02
[patent_title] => TRANSISTOR DEVICE WITH SINKER CONTACTS AND METHODS FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/322274
[patent_app_country] => US
[patent_app_date] => 2021-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3769
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322274
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/322274 | TRANSISTOR DEVICE WITH SINKER CONTACTS AND METHODS FOR MANUFACTURING THE SAME | May 16, 2021 | Pending |
Array
(
[id] => 18431707
[patent_doc_number] => 11676937
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Flexible sinter tool for bonding semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 17/307028
[patent_app_country] => US
[patent_app_date] => 2021-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 5100
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17307028
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/307028 | Flexible sinter tool for bonding semiconductor devices | May 3, 2021 | Issued |
Array
(
[id] => 17257475
[patent_doc_number] => 20210370460
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-02
[patent_title] => WAFER PROCESSING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/243850
[patent_app_country] => US
[patent_app_date] => 2021-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7406
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17243850
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/243850 | Wafer processing method | Apr 28, 2021 | Issued |
Array
(
[id] => 17949261
[patent_doc_number] => 20220336280
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => METHOD OF MANUFACTURING MICROELECTRONIC DEVICES AND RELATED MICROELECTRONIC DEVICES, TOOLS, AND APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/231313
[patent_app_country] => US
[patent_app_date] => 2021-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9656
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231313
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/231313 | METHOD OF MANUFACTURING MICROELECTRONIC DEVICES AND RELATED MICROELECTRONIC DEVICES, TOOLS, AND APPARATUS | Apr 14, 2021 | Pending |
Array
(
[id] => 17318804
[patent_doc_number] => 20210407854
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => SEMICONDUCTOR DIE FORMING AND PACKAGING METHOD USING ULTRASHORT PULSE LASER MICROMACHINING
[patent_app_type] => utility
[patent_app_number] => 17/231074
[patent_app_country] => US
[patent_app_date] => 2021-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8391
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231074
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/231074 | Semiconductor die forming and packaging method using ultrashort pulse laser micromachining | Apr 14, 2021 | Issued |
Array
(
[id] => 16981762
[patent_doc_number] => 20210225999
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-22
[patent_title] => ADJUSTABLE MULTI-TURN MAGNETIC COUPLING DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/222816
[patent_app_country] => US
[patent_app_date] => 2021-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9355
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222816
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/222816 | Adjustable multi-turn magnetic coupling device | Apr 4, 2021 | Issued |
Array
(
[id] => 16966186
[patent_doc_number] => 20210217685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-15
[patent_title] => OVERMOLDED MICROELECTRONIC PACKAGES CONTAINING KNURLED FLANGES AND METHODS FOR THE PRODUCTION THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/213641
[patent_app_country] => US
[patent_app_date] => 2021-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9747
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213641
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/213641 | Overmolded microelectronic packages containing knurled flanges and methods for the production thereof | Mar 25, 2021 | Issued |
Array
(
[id] => 18623861
[patent_doc_number] => 11756917
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-12
[patent_title] => Method for processing a semiconductor wafer, semiconductor wafer, clip and semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/202990
[patent_app_country] => US
[patent_app_date] => 2021-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 7512
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202990
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/202990 | Method for processing a semiconductor wafer, semiconductor wafer, clip and semiconductor device | Mar 15, 2021 | Issued |
Array
(
[id] => 18580668
[patent_doc_number] => 11737215
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-22
[patent_title] => Printed circuit film, display device, and method of fabricating printed circuit film
[patent_app_type] => utility
[patent_app_number] => 17/198197
[patent_app_country] => US
[patent_app_date] => 2021-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 11838
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198197
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/198197 | Printed circuit film, display device, and method of fabricating printed circuit film | Mar 9, 2021 | Issued |
Array
(
[id] => 16920567
[patent_doc_number] => 20210193659
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/195019
[patent_app_country] => US
[patent_app_date] => 2021-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9640
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195019
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/195019 | Semiconductor device | Mar 7, 2021 | Issued |
Array
(
[id] => 18431737
[patent_doc_number] => 11676969
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Semiconductor-on-insulator wafer having a composite insulator layer
[patent_app_type] => utility
[patent_app_number] => 17/192333
[patent_app_country] => US
[patent_app_date] => 2021-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 8600
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192333
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/192333 | Semiconductor-on-insulator wafer having a composite insulator layer | Mar 3, 2021 | Issued |
Array
(
[id] => 18277033
[patent_doc_number] => 11615981
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-28
[patent_title] => Isolator
[patent_app_type] => utility
[patent_app_number] => 17/191776
[patent_app_country] => US
[patent_app_date] => 2021-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4692
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 271
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191776
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/191776 | Isolator | Mar 3, 2021 | Issued |
Array
(
[id] => 17100122
[patent_doc_number] => 20210287913
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-16
[patent_title] => ETCHING METHOD AND ELEMENT CHIP MANUFACTURING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/188005
[patent_app_country] => US
[patent_app_date] => 2021-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12844
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17188005
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/188005 | Etching method and element chip manufacturing method | Feb 28, 2021 | Issued |
Array
(
[id] => 18766937
[patent_doc_number] => 11817346
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-14
[patent_title] => Isolator
[patent_app_type] => utility
[patent_app_number] => 17/181147
[patent_app_country] => US
[patent_app_date] => 2021-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 37
[patent_no_of_words] => 8048
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181147
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/181147 | Isolator | Feb 21, 2021 | Issued |
Array
(
[id] => 17660743
[patent_doc_number] => 20220181208
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => SEMICONDUCTOR DEVICE WITH REDUCED STRESS DIE PICK AND PLACE
[patent_app_type] => utility
[patent_app_number] => 17/174802
[patent_app_country] => US
[patent_app_date] => 2021-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4102
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174802
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/174802 | Semiconductor device with reduced stress die pick and place | Feb 11, 2021 | Issued |
Array
(
[id] => 18415991
[patent_doc_number] => 11670537
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-06
[patent_title] => Method of manufacturing semiconductor device having buried gate electrodes
[patent_app_type] => utility
[patent_app_number] => 17/167170
[patent_app_country] => US
[patent_app_date] => 2021-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 30
[patent_no_of_words] => 11981
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167170
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/167170 | Method of manufacturing semiconductor device having buried gate electrodes | Feb 3, 2021 | Issued |
Array
(
[id] => 18494169
[patent_doc_number] => 11699590
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-11
[patent_title] => Copper electrodeposition sequence for the filling of cobalt lined features
[patent_app_type] => utility
[patent_app_number] => 17/158963
[patent_app_country] => US
[patent_app_date] => 2021-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4297
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158963
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/158963 | Copper electrodeposition sequence for the filling of cobalt lined features | Jan 25, 2021 | Issued |