
Stella Eun Higgs
Examiner (ID: 3981, Phone: (571)270-5891 , Office: P/2179 )
| Most Active Art Unit | 2179 |
| Art Unit(s) | 2189, 4132, 2179, 3681, 3686, 3628 |
| Total Applications | 416 |
| Issued Applications | 148 |
| Pending Applications | 61 |
| Abandoned Applications | 209 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17025202
[patent_doc_number] => 20210249074
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-12
[patent_title] => NONVOLATILE MEMORY APPARATUS FOR PERFORMING A READ OPERATION AND A METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/245870
[patent_app_country] => US
[patent_app_date] => 2021-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6542
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245870
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/245870 | Nonvolatile memory apparatus for performing a read operation and a method of operating the same | Apr 29, 2021 | Issued |
Array
(
[id] => 17763295
[patent_doc_number] => 20220236907
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => DEVICES FOR GENERATING MODE COMMANDS
[patent_app_type] => utility
[patent_app_number] => 17/240330
[patent_app_country] => US
[patent_app_date] => 2021-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11863
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240330
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/240330 | Devices for generating mode commands | Apr 25, 2021 | Issued |
Array
(
[id] => 18415818
[patent_doc_number] => 11670363
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-06
[patent_title] => Multi-tier memory architecture
[patent_app_type] => utility
[patent_app_number] => 17/238683
[patent_app_country] => US
[patent_app_date] => 2021-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6153
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17238683
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/238683 | Multi-tier memory architecture | Apr 22, 2021 | Issued |
Array
(
[id] => 17009236
[patent_doc_number] => 20210240397
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-05
[patent_title] => ELECTRONIC APPARATUS AND METHOD OF MANAGING READ LEVELS OF FLASH MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/235935
[patent_app_country] => US
[patent_app_date] => 2021-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3304
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235935
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235935 | Electronic apparatus and method of managing read levels of flash memory | Apr 20, 2021 | Issued |
Array
(
[id] => 18047714
[patent_doc_number] => 11521672
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-06
[patent_title] => Semiconductor device and memory system
[patent_app_type] => utility
[patent_app_number] => 17/230519
[patent_app_country] => US
[patent_app_date] => 2021-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 25
[patent_no_of_words] => 11916
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230519
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/230519 | Semiconductor device and memory system | Apr 13, 2021 | Issued |
Array
(
[id] => 17216303
[patent_doc_number] => 20210349641
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-11
[patent_title] => MEMORY CIRCUIT AND MEMORY REPAIR METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/226518
[patent_app_country] => US
[patent_app_date] => 2021-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3312
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17226518
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/226518 | Memory circuit and memory repair method thereof | Apr 8, 2021 | Issued |
Array
(
[id] => 17115326
[patent_doc_number] => 20210295923
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-23
[patent_title] => INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/224698
[patent_app_country] => US
[patent_app_date] => 2021-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7319
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224698
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/224698 | INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES | Apr 6, 2021 | Abandoned |
Array
(
[id] => 17447851
[patent_doc_number] => 20220068356
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-03
[patent_title] => MULTI-LEVEL SIGNAL RECEIVERS AND MEMORY SYSTEMS INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/223458
[patent_app_country] => US
[patent_app_date] => 2021-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15035
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223458
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/223458 | Multi-level signal receivers and memory systems including the same | Apr 5, 2021 | Issued |
Array
(
[id] => 18088382
[patent_doc_number] => 11538521
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-27
[patent_title] => Adaptive application of voltage pulses to stabilize memory cell voltage levels
[patent_app_type] => utility
[patent_app_number] => 17/222949
[patent_app_country] => US
[patent_app_date] => 2021-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 9836
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222949
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/222949 | Adaptive application of voltage pulses to stabilize memory cell voltage levels | Apr 4, 2021 | Issued |
Array
(
[id] => 17917180
[patent_doc_number] => 20220319576
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => APPARATUSES AND METHODS FOR SINGLE-ENDED GLOBAL AND LOCAL INPUT/OUTPUT ARCHITECTURE
[patent_app_type] => utility
[patent_app_number] => 17/217981
[patent_app_country] => US
[patent_app_date] => 2021-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8561
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217981
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/217981 | Apparatuses and methods for single-ended global and local input/output architecture | Mar 29, 2021 | Issued |
Array
(
[id] => 18031800
[patent_doc_number] => 11514995
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-29
[patent_title] => Memory sub-system self-testing operations
[patent_app_type] => utility
[patent_app_number] => 17/211133
[patent_app_country] => US
[patent_app_date] => 2021-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 10402
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211133
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/211133 | Memory sub-system self-testing operations | Mar 23, 2021 | Issued |
Array
(
[id] => 17485652
[patent_doc_number] => 20220093156
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-24
[patent_title] => MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/205239
[patent_app_country] => US
[patent_app_date] => 2021-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4339
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17205239
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/205239 | Memory system | Mar 17, 2021 | Issued |
Array
(
[id] => 17886128
[patent_doc_number] => 20220301605
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION
[patent_app_type] => utility
[patent_app_number] => 17/204649
[patent_app_country] => US
[patent_app_date] => 2021-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8602
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204649
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/204649 | Compute-in-memory with ternary activation | Mar 16, 2021 | Issued |
Array
(
[id] => 17886128
[patent_doc_number] => 20220301605
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION
[patent_app_type] => utility
[patent_app_number] => 17/204649
[patent_app_country] => US
[patent_app_date] => 2021-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8602
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204649
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/204649 | Compute-in-memory with ternary activation | Mar 16, 2021 | Issued |
Array
(
[id] => 17886128
[patent_doc_number] => 20220301605
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION
[patent_app_type] => utility
[patent_app_number] => 17/204649
[patent_app_country] => US
[patent_app_date] => 2021-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8602
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204649
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/204649 | Compute-in-memory with ternary activation | Mar 16, 2021 | Issued |
Array
(
[id] => 17886128
[patent_doc_number] => 20220301605
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION
[patent_app_type] => utility
[patent_app_number] => 17/204649
[patent_app_country] => US
[patent_app_date] => 2021-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8602
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204649
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/204649 | Compute-in-memory with ternary activation | Mar 16, 2021 | Issued |
Array
(
[id] => 18031791
[patent_doc_number] => 11514986
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-29
[patent_title] => Memory system and semiconductor memory device
[patent_app_type] => utility
[patent_app_number] => 17/202627
[patent_app_country] => US
[patent_app_date] => 2021-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 44
[patent_no_of_words] => 30611
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202627
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/202627 | Memory system and semiconductor memory device | Mar 15, 2021 | Issued |
Array
(
[id] => 18235750
[patent_doc_number] => 11600314
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-07
[patent_title] => Apparatuses and methods for sketch circuits for refresh binning
[patent_app_type] => utility
[patent_app_number] => 17/201941
[patent_app_country] => US
[patent_app_date] => 2021-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 9484
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201941
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/201941 | Apparatuses and methods for sketch circuits for refresh binning | Mar 14, 2021 | Issued |
Array
(
[id] => 17893051
[patent_doc_number] => 11456030
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-27
[patent_title] => Static random access memory SRAM unit and related apparatus
[patent_app_type] => utility
[patent_app_number] => 17/187455
[patent_app_country] => US
[patent_app_date] => 2021-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 12330
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 440
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187455
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/187455 | Static random access memory SRAM unit and related apparatus | Feb 25, 2021 | Issued |
Array
(
[id] => 17969945
[patent_doc_number] => 11487476
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-01
[patent_title] => Semiconductor memory device
[patent_app_type] => utility
[patent_app_number] => 17/184674
[patent_app_country] => US
[patent_app_date] => 2021-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 25112
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184674
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/184674 | Semiconductor memory device | Feb 24, 2021 | Issued |