Search

Stella Eun Higgs

Examiner (ID: 3981, Phone: (571)270-5891 , Office: P/2179 )

Most Active Art Unit
2179
Art Unit(s)
2189, 4132, 2179, 3681, 3686, 3628
Total Applications
416
Issued Applications
148
Pending Applications
61
Abandoned Applications
209

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17302745 [patent_doc_number] => 20210398584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => METHOD AND CIRCUIT FOR PROTECTING A DRAM MEMORY DEVICE FROM THE ROW HAMMER EFFECT [patent_app_type] => utility [patent_app_number] => 17/098044 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098044 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098044
Method and circuit for protecting a DRAM memory device from the row hammer effect Nov 12, 2020 Issued
Array ( [id] => 17757974 [patent_doc_number] => 11398272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/095000 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6964 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095000
Semiconductor memory device Nov 10, 2020 Issued
Array ( [id] => 16936109 [patent_doc_number] => 20210201998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => NONVOLATILE SRAM [patent_app_type] => utility [patent_app_number] => 17/094307 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6491 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094307 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094307
Nonvolatile SRAM Nov 9, 2020 Issued
Array ( [id] => 17606906 [patent_doc_number] => 11335398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Integrated circuit and memory [patent_app_type] => utility [patent_app_number] => 17/084910 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6218 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084910 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/084910
Integrated circuit and memory Oct 29, 2020 Issued
Array ( [id] => 16981189 [patent_doc_number] => 20210225426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => MEMORY DEVICE TRANSMITTING AND RECEIVING DATA AT HIGH SPEED AND LOW POWER [patent_app_type] => utility [patent_app_number] => 17/084345 [patent_app_country] => US [patent_app_date] => 2020-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/084345
Memory device transmitting and receiving data at high speed and low power Oct 28, 2020 Issued
Array ( [id] => 17469973 [patent_doc_number] => 11276455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-15 [patent_title] => Systems and methods for memory device power off [patent_app_type] => utility [patent_app_number] => 17/082964 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6249 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/082964
Systems and methods for memory device power off Oct 27, 2020 Issued
Array ( [id] => 16765281 [patent_doc_number] => 20210110863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => SENSE AMPLIFIER WITH LOWER OFFSET AND INCREASED SPEED [patent_app_type] => utility [patent_app_number] => 17/078806 [patent_app_country] => US [patent_app_date] => 2020-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078806 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/078806
Sense amplifier with lower offset and increased speed Oct 22, 2020 Issued
Array ( [id] => 18039707 [patent_doc_number] => 20220383924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => TWO BIT MEMORY DEVICE AND METHOD FOR OPERATING THE TWO-BIT MEMORY DEVICE AND ELECTRONIC COMPONENT [patent_app_type] => utility [patent_app_number] => 17/771200 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17771200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/771200
Two bit memory device and method for operating the two-bit memory device and electronic component Oct 19, 2020 Issued
Array ( [id] => 18219327 [patent_doc_number] => 11594273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Row hammer detection and avoidance [patent_app_type] => utility [patent_app_number] => 17/070865 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5859 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070865 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/070865
Row hammer detection and avoidance Oct 13, 2020 Issued
Array ( [id] => 16730917 [patent_doc_number] => 20210098065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => ARCHITECTURE FOR 3-D NAND MEMORY [patent_app_type] => utility [patent_app_number] => 17/067577 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067577 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/067577
Architecture for 3-D NAND memory Oct 8, 2020 Issued
Array ( [id] => 17573921 [patent_doc_number] => 11322195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Compute in memory system [patent_app_type] => utility [patent_app_number] => 17/034701 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034701
Compute in memory system Sep 27, 2020 Issued
Array ( [id] => 17508831 [patent_doc_number] => 20220101934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => MEMORY WITH CELLS HAVING MULTIPLE SELECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/032913 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17032913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/032913
Memory with cells having multiple select transistors Sep 24, 2020 Issued
Array ( [id] => 16617342 [patent_doc_number] => 20210035995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => MEMORY DEVICE INCLUDING PASS TRANSISTORS IN MEMORY TIERS [patent_app_type] => utility [patent_app_number] => 17/027399 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027399 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027399
Memory device including pass transistors in memory tiers Sep 20, 2020 Issued
Array ( [id] => 17173823 [patent_doc_number] => 20210327494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => HARDWARE-ASSISTED DYNAMIC RANDOM ACCESS MEMORY (DRAM) ROW MERGING [patent_app_type] => utility [patent_app_number] => 17/025157 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025157 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025157
Hardware-assisted dynamic random access memory (DRAM) row merging Sep 17, 2020 Issued
Array ( [id] => 17346827 [patent_doc_number] => 20220013158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => MAGNETORESISTIVE RANDOM ACCESS MEMORY AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/023599 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023599 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/023599
Magnetoresistive random access memory and operating method thereof Sep 16, 2020 Issued
Array ( [id] => 17878370 [patent_doc_number] => 11450391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Multi-tier threshold voltage offset bin calibration [patent_app_type] => utility [patent_app_number] => 16/948359 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11279 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948359 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/948359
Multi-tier threshold voltage offset bin calibration Sep 14, 2020 Issued
Array ( [id] => 16560114 [patent_doc_number] => 20210005263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => OPERATIONS ON MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/019582 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019582 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/019582
Operations on memory cells Sep 13, 2020 Issued
Array ( [id] => 18480991 [patent_doc_number] => 11694742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Apparatuses and methods for internal voltage generating circuits [patent_app_type] => utility [patent_app_number] => 17/018339 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10818 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018339 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018339
Apparatuses and methods for internal voltage generating circuits Sep 10, 2020 Issued
Array ( [id] => 17253852 [patent_doc_number] => 11189348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/009389 [patent_app_country] => US [patent_app_date] => 2020-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17009389 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/009389
Semiconductor memory device Aug 31, 2020 Issued
Array ( [id] => 17121915 [patent_doc_number] => 11133055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-28 [patent_title] => Electronic device to perform read operation and mode register read operation [patent_app_type] => utility [patent_app_number] => 17/009413 [patent_app_country] => US [patent_app_date] => 2020-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17009413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/009413
Electronic device to perform read operation and mode register read operation Aug 31, 2020 Issued
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