Search

Stella Eun Higgs

Examiner (ID: 3981, Phone: (571)270-5891 , Office: P/2179 )

Most Active Art Unit
2179
Art Unit(s)
2189, 4132, 2179, 3681, 3686, 3628
Total Applications
416
Issued Applications
148
Pending Applications
61
Abandoned Applications
209

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16255436 [patent_doc_number] => 20200264810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => HIGH DENSITY FRACTIONAL BIT SOLID STATE DRIVES USING CODED SET PARTITIONS [patent_app_type] => utility [patent_app_number] => 16/796296 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796296 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796296
High density fractional bit solid state drives using coded set partitions Feb 19, 2020 Issued
Array ( [id] => 16879208 [patent_doc_number] => 11029346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Monitoring load operation [patent_app_type] => utility [patent_app_number] => 16/795741 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6782 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16795741 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/795741
Monitoring load operation Feb 19, 2020 Issued
Array ( [id] => 17379812 [patent_doc_number] => 11237828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Secure matrix space with partitions for concurrent use [patent_app_type] => utility [patent_app_number] => 16/783125 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12209 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16783125 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/783125
Secure matrix space with partitions for concurrent use Feb 4, 2020 Issued
Array ( [id] => 17092671 [patent_doc_number] => 11120865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Apparatuses and methods for implementing access line loads for sense amplifiers for open access line sensing [patent_app_type] => utility [patent_app_number] => 16/746778 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4438 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746778 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746778
Apparatuses and methods for implementing access line loads for sense amplifiers for open access line sensing Jan 16, 2020 Issued
Array ( [id] => 17283915 [patent_doc_number] => 11200955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Non-volatile memory device and memory system including the same and program method thereof [patent_app_type] => utility [patent_app_number] => 16/734799 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 422 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734799 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/734799
Non-volatile memory device and memory system including the same and program method thereof Jan 5, 2020 Issued
Array ( [id] => 17359618 [patent_doc_number] => 20220020414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => PAGE POLICIES FOR SIGNAL DEVELOPMENT CACHING IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/414823 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17414823 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/414823
Page policies for signal development caching in a memory device Dec 19, 2019 Issued
Array ( [id] => 16911447 [patent_doc_number] => 11043497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-22 [patent_title] => Integrated memory having non-ohmic devices and capacitors [patent_app_type] => utility [patent_app_number] => 16/721006 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5356 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721006
Integrated memory having non-ohmic devices and capacitors Dec 18, 2019 Issued
Array ( [id] => 16781415 [patent_doc_number] => 20210118494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => STATIC RANDOM-ACCESS MEMORY (SRAM) SYSTEM WITH DELAY TUNING AND CONTROL AND A METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/720888 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720888 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/720888
Static random-access memory (SRAM) system with delay tuning and control and a method thereof Dec 18, 2019 Issued
Array ( [id] => 16707434 [patent_doc_number] => 10957376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-23 [patent_title] => Refresh testing circuit and method [patent_app_type] => utility [patent_app_number] => 16/719930 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3205 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719930 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719930
Refresh testing circuit and method Dec 17, 2019 Issued
Array ( [id] => 16609059 [patent_doc_number] => 10910072 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Accurate self-calibrated negative to positive voltage conversion circuit and method [patent_app_type] => utility [patent_app_number] => 16/717168 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717168 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717168
Accurate self-calibrated negative to positive voltage conversion circuit and method Dec 16, 2019 Issued
Array ( [id] => 17062940 [patent_doc_number] => 11107549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => At-risk memory location identification and management [patent_app_type] => utility [patent_app_number] => 16/715468 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 12961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715468 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715468
At-risk memory location identification and management Dec 15, 2019 Issued
Array ( [id] => 16097855 [patent_doc_number] => 20200202914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => SPIN ORBIT TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/716024 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716024 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/716024
Spin orbit torque magnetoresistive random access memory device Dec 15, 2019 Issued
Array ( [id] => 16773762 [patent_doc_number] => 10984881 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-20 [patent_title] => Memory sub-system self-testing operations [patent_app_type] => utility [patent_app_number] => 16/713108 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10375 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713108 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/713108
Memory sub-system self-testing operations Dec 12, 2019 Issued
Array ( [id] => 16119203 [patent_doc_number] => 20200211624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => INTEGRATED CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 16/713336 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713336 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/713336
Integrated circuit and memory Dec 12, 2019 Issued
Array ( [id] => 17955194 [patent_doc_number] => 11481299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Transmission of data for a machine learning operation using different microbumps [patent_app_type] => utility [patent_app_number] => 16/703142 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 17824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703142 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703142
Transmission of data for a machine learning operation using different microbumps Dec 3, 2019 Issued
Array ( [id] => 17309977 [patent_doc_number] => 11211101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Differential amplifier schemes for sensing memory cells [patent_app_type] => utility [patent_app_number] => 16/702422 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 31615 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702422 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/702422
Differential amplifier schemes for sensing memory cells Dec 2, 2019 Issued
Array ( [id] => 16873279 [patent_doc_number] => 20210166746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => WRITE OPERATION TECHNIQUES FOR MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/700948 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16700948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/700948
Write operation techniques for memory systems Dec 1, 2019 Issued
Array ( [id] => 16502290 [patent_doc_number] => 10867684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-15 [patent_title] => Driving access lines to target voltage levels [patent_app_type] => utility [patent_app_number] => 16/699882 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 12866 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699882 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/699882
Driving access lines to target voltage levels Dec 1, 2019 Issued
Array ( [id] => 16873275 [patent_doc_number] => 20210166742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => PROCESSING MULTI-CYCLE COMMANDS IN MEMORY DEVICES, AND RELATED METHODS, DEVICES, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/700212 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16700212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/700212
Processing multi-cycle commands in memory devices, and related methods, devices, and systems Dec 1, 2019 Issued
Array ( [id] => 17318507 [patent_doc_number] => 20210407557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => Sensitivity Amplifier, Its Control Method, Memory and Its Read-Write Circuit [patent_app_type] => utility [patent_app_number] => 17/280818 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17280818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/280818
Sensitivity amplifier, its control method, memory and its read-write circuit Nov 26, 2019 Issued
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