Search

Stella Eun Higgs

Examiner (ID: 3981, Phone: (571)270-5891 , Office: P/2179 )

Most Active Art Unit
2179
Art Unit(s)
2189, 4132, 2179, 3681, 3686, 3628
Total Applications
416
Issued Applications
148
Pending Applications
61
Abandoned Applications
209

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19712384 [patent_doc_number] => 20250022526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => CLOCK GENERATION CIRCUITS FOR MEMORY DEVICES WITH BUILT-IN SELF TEST [patent_app_type] => utility [patent_app_number] => 18/352815 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352815 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352815
CLOCK GENERATION CIRCUITS FOR MEMORY DEVICES WITH BUILT-IN SELF TEST Jul 13, 2023 Pending
Array ( [id] => 18907838 [patent_doc_number] => 20240023323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => SEMICONDUCTOR MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/221898 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221898 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221898
SEMICONDUCTOR MEMORY STRUCTURE Jul 13, 2023 Pending
Array ( [id] => 18905742 [patent_doc_number] => 20240021227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => OUTPUT CONTROL INTERFACE CIRCUIT FOR STATIC RANDOM ACCESS MEMORY AND OUTPUT CONTROL METHOD FOR THE SAME [patent_app_type] => utility [patent_app_number] => 18/221642 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221642 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221642
Output control interface circuit for static random access memory and output control method for the same Jul 12, 2023 Issued
Array ( [id] => 20482635 [patent_doc_number] => 12531111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Semiconductor package including memory die stack having clock signal shared by lower and upper bytes [patent_app_type] => utility [patent_app_number] => 18/348591 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4618 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348591 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348591
Semiconductor package including memory die stack having clock signal shared by lower and upper bytes Jul 6, 2023 Issued
Array ( [id] => 19191135 [patent_doc_number] => 20240170048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/219369 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219369 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/219369
Nonvolatile memory device Jul 6, 2023 Issued
Array ( [id] => 20258847 [patent_doc_number] => 12431210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Selecting read reference voltage using historical decoding information [patent_app_type] => utility [patent_app_number] => 18/217959 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2830 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217959 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/217959
Selecting read reference voltage using historical decoding information Jul 2, 2023 Issued
Array ( [id] => 19873527 [patent_doc_number] => 12266396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Input data pre-alignment circuit capable of performing a first-in first-out signal alignment mechanism [patent_app_type] => utility [patent_app_number] => 18/212172 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4485 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212172 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/212172
Input data pre-alignment circuit capable of performing a first-in first-out signal alignment mechanism Jun 19, 2023 Issued
Array ( [id] => 20596292 [patent_doc_number] => 12580015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Memory device having architecture of voltage driver circuit and decoupling capacitor [patent_app_type] => utility [patent_app_number] => 18/337507 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337507 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337507
Memory device having architecture of voltage driver circuit and decoupling capacitor Jun 19, 2023 Issued
Array ( [id] => 19704706 [patent_doc_number] => 12198752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => High density memory with reference memory using grouped cells and corresponding operations [patent_app_type] => utility [patent_app_number] => 18/206422 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 12866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206422 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206422
High density memory with reference memory using grouped cells and corresponding operations Jun 5, 2023 Issued
Array ( [id] => 18820785 [patent_doc_number] => 20230395126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => ROW HAMMER MITIGATION USING HIERARCHICAL DETECTORS [patent_app_type] => utility [patent_app_number] => 18/204786 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18204786 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/204786
Row hammer mitigation using hierarchical detectors May 31, 2023 Issued
Array ( [id] => 19351300 [patent_doc_number] => 20240260264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR DEVICE HAVING CHANNEL ISOLATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/326590 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326590 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/326590
Semiconductor device having channel isolation structure May 30, 2023 Issued
Array ( [id] => 19604470 [patent_doc_number] => 20240395350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => Extending Dual Inline Memory Module (DIMM) Lifespans Based on Fault Characterization and Optimized Corrective Action [patent_app_type] => utility [patent_app_number] => 18/200322 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200322 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/200322
Extending dual inline memory module (DIMM) lifespans based on fault characterization and optimized corrective action May 21, 2023 Issued
Array ( [id] => 20175713 [patent_doc_number] => 12394466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Memory device, memory system including the same and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/319655 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 4459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319655 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/319655
Memory device, memory system including the same and method of operating the same May 17, 2023 Issued
Array ( [id] => 20243940 [patent_doc_number] => 12424270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Semiconductor memory device and memory module having various operation modes [patent_app_type] => utility [patent_app_number] => 18/315571 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315571 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315571
Semiconductor memory device and memory module having various operation modes May 10, 2023 Issued
Array ( [id] => 20243941 [patent_doc_number] => 12424271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Semiconductor apparatus and semiconductor system having lun selection cycle, and operating method of semiconductor system [patent_app_type] => utility [patent_app_number] => 18/297375 [patent_app_country] => US [patent_app_date] => 2023-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4767 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18297375 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/297375
Semiconductor apparatus and semiconductor system having lun selection cycle, and operating method of semiconductor system Apr 6, 2023 Issued
Array ( [id] => 18696067 [patent_doc_number] => 20230326498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM HAVING INDEPENDENT DATA INPUT/OUTPUT PERIOD, AND OPERATING METHOD OF THE SEMICONDUCTOR SYSTEM [patent_app_type] => utility [patent_app_number] => 18/297277 [patent_app_country] => US [patent_app_date] => 2023-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -35 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18297277 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/297277
Semiconductor apparatus and semiconductor system having independent data input/output period, and operating method of the semiconductor system Apr 6, 2023 Issued
Array ( [id] => 20690274 [patent_doc_number] => 12620431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Refresh management selection [patent_app_type] => utility [patent_app_number] => 18/121246 [patent_app_country] => US [patent_app_date] => 2023-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18121246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/121246
Refresh management selection Mar 13, 2023 Issued
Array ( [id] => 19452377 [patent_doc_number] => 20240312507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => DEVICES, METHODS, AND SYSTEMS FOR CALIBRATING A SENSING CAPACITOR USED IN A SENSING CIRCUIT FOR READING MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/182562 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182562 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/182562
Devices, methods, and systems for calibrating a sensing capacitor used in a sensing circuit for reading memory cells Mar 12, 2023 Issued
Array ( [id] => 18655360 [patent_doc_number] => 20230301218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => VARIABLE RESISTANCE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/119970 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119970
Variable resistance memory device Mar 9, 2023 Issued
Array ( [id] => 18661025 [patent_doc_number] => 20230307038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => Memory controller and method for calibrating data reception window [patent_app_type] => utility [patent_app_number] => 18/119808 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119808 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119808
Memory controller and method for calibrating data reception window Mar 8, 2023 Issued
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