Search

Stephanie A. N. Mcneil

Examiner (ID: 4048, Phone: (571)270-5250 , Office: P/1653 )

Most Active Art Unit
1653
Art Unit(s)
1653
Total Applications
397
Issued Applications
37
Pending Applications
85
Abandoned Applications
294

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14366471 [patent_doc_number] => 10304547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Memory device and clock training method thereof [patent_app_type] => utility [patent_app_number] => 15/700324 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9099 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700324 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700324
Memory device and clock training method thereof Sep 10, 2017 Issued
Array ( [id] => 14063541 [patent_doc_number] => 10236071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-19 [patent_title] => Dual-bit ROM cell with virtual ground line and programmable metal track [patent_app_type] => utility [patent_app_number] => 15/700152 [patent_app_country] => US [patent_app_date] => 2017-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9560 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700152 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700152
Dual-bit ROM cell with virtual ground line and programmable metal track Sep 9, 2017 Issued
Array ( [id] => 14603077 [patent_doc_number] => 10354732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => NAND temperature data management [patent_app_type] => utility [patent_app_number] => 15/690920 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13761 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690920 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690920
NAND temperature data management Aug 29, 2017 Issued
Array ( [id] => 12895555 [patent_doc_number] => 20180190360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => DEVICE FOR DETECTING LEAKAGE CURRENT AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/690768 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690768 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690768
Device for detecting leakage current and memory device Aug 29, 2017 Issued
Array ( [id] => 13769023 [patent_doc_number] => 10176858 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-08 [patent_title] => Adjusting instruction delays to the latch path in DDR5 DRAM [patent_app_type] => utility [patent_app_number] => 15/691394 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5178 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691394
Adjusting instruction delays to the latch path in DDR5 DRAM Aug 29, 2017 Issued
Array ( [id] => 14459363 [patent_doc_number] => 10325652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Cell programming verification [patent_app_type] => utility [patent_app_number] => 15/690148 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6204 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690148 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690148
Cell programming verification Aug 28, 2017 Issued
Array ( [id] => 13893119 [patent_doc_number] => 10199111 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-05 [patent_title] => Memory devices with read level calibration [patent_app_type] => utility [patent_app_number] => 15/669055 [patent_app_country] => US [patent_app_date] => 2017-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6994 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15669055 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/669055
Memory devices with read level calibration Aug 3, 2017 Issued
Array ( [id] => 14204611 [patent_doc_number] => 10269424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Semiconductor memory apparatus [patent_app_type] => utility [patent_app_number] => 15/669689 [patent_app_country] => US [patent_app_date] => 2017-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15669689 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/669689
Semiconductor memory apparatus Aug 3, 2017 Issued
Array ( [id] => 13256699 [patent_doc_number] => 10141043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-27 [patent_title] => DRAM and method for managing power thereof [patent_app_type] => utility [patent_app_number] => 15/657592 [patent_app_country] => US [patent_app_date] => 2017-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6742 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15657592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/657592
DRAM and method for managing power thereof Jul 23, 2017 Issued
Array ( [id] => 13272357 [patent_doc_number] => 10148269 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-04 [patent_title] => Dynamic termination edge control [patent_app_type] => utility [patent_app_number] => 15/658276 [patent_app_country] => US [patent_app_date] => 2017-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15658276 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/658276
Dynamic termination edge control Jul 23, 2017 Issued
Array ( [id] => 12129073 [patent_doc_number] => 20180012659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'Tunnel FET Based Non-Volatile Memory Boosted By Vertical Band-to-Band Tunneling' [patent_app_type] => utility [patent_app_number] => 15/641472 [patent_app_country] => US [patent_app_date] => 2017-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 5648 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15641472 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/641472
Tunnel FET Based Non-Volatile Memory Boosted By Vertical Band-to-Band Tunneling Jul 4, 2017 Abandoned
Array ( [id] => 13799073 [patent_doc_number] => 20190013075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => MULTIFUNCTIONAL MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 15/641736 [patent_app_country] => US [patent_app_date] => 2017-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15641736 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/641736
Multifunctional memory cells Jul 4, 2017 Issued
Array ( [id] => 12263549 [patent_doc_number] => 20180082745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/640568 [patent_app_country] => US [patent_app_date] => 2017-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 23027 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640568 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/640568
Semiconductor device Jul 1, 2017 Issued
Array ( [id] => 13784949 [patent_doc_number] => 20190006013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => SELECTIVE BODY RESET OPERATION FOR THREE DIMENSIONAL (3D) NAND MEMORY [patent_app_type] => utility [patent_app_number] => 15/640518 [patent_app_country] => US [patent_app_date] => 2017-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640518 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/640518
Selective body reset operation for three dimensional (3D) NAND memory Jun 30, 2017 Issued
Array ( [id] => 16279903 [patent_doc_number] => 10762939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Computer memory [patent_app_type] => utility [patent_app_number] => 15/640530 [patent_app_country] => US [patent_app_date] => 2017-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7056 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640530 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/640530
Computer memory Jun 30, 2017 Issued
Array ( [id] => 13242531 [patent_doc_number] => 10134472 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-20 [patent_title] => Floating gate architecture for deep neural network application [patent_app_type] => utility [patent_app_number] => 15/640190 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 8215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640190 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/640190
Floating gate architecture for deep neural network application Jun 29, 2017 Issued
Array ( [id] => 13201041 [patent_doc_number] => 10115440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Word line contact regions for three-dimensional non-volatile memory [patent_app_type] => utility [patent_app_number] => 15/625848 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 11710 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625848 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625848
Word line contact regions for three-dimensional non-volatile memory Jun 15, 2017 Issued
Array ( [id] => 13215161 [patent_doc_number] => 10121959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-06 [patent_title] => FDSOI STT-MRAM design [patent_app_type] => utility [patent_app_number] => 15/625272 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3835 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625272 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625272
FDSOI STT-MRAM design Jun 15, 2017 Issued
Array ( [id] => 12154521 [patent_doc_number] => 20180025785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'ONE-TIME PROGRAMMABLE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/619300 [patent_app_country] => US [patent_app_date] => 2017-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15619300 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/619300
One-time programmable memory device Jun 8, 2017 Issued
Array ( [id] => 13613073 [patent_doc_number] => 20180358086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => Write Operation Scheme for SRAM [patent_app_type] => utility [patent_app_number] => 15/619332 [patent_app_country] => US [patent_app_date] => 2017-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15619332 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/619332
Write operation scheme for SRAM Jun 8, 2017 Issued
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