Search

Stephanie P. Duclair

Examiner (ID: 16086, Phone: (571)270-5502 , Office: P/1713 )

Most Active Art Unit
1713
Art Unit(s)
1792, 1713
Total Applications
887
Issued Applications
572
Pending Applications
88
Abandoned Applications
241

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19900176 [patent_doc_number] => 12278110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Bias voltage modulation approach for SiO/SiN layer alternating etch process [patent_app_type] => utility [patent_app_number] => 17/572397 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572397
Bias voltage modulation approach for SiO/SiN layer alternating etch process Jan 9, 2022 Issued
Array ( [id] => 18500278 [patent_doc_number] => 20230223063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => SEMICONDUCTOR MEMORY STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/571945 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571945
Semiconductor memory structure and method for forming the semiconductor memory structure Jan 9, 2022 Issued
Array ( [id] => 19828726 [patent_doc_number] => 12249517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Manufacturing method of semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/646487 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 4810 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646487 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646487
Manufacturing method of semiconductor structure Dec 29, 2021 Issued
Array ( [id] => 19886835 [patent_doc_number] => 12272562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Oxygen and iodine-containing hydrofluorocarbon compound for etching semiconductor structures [patent_app_type] => utility [patent_app_number] => 17/555094 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 15253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555094 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555094
Oxygen and iodine-containing hydrofluorocarbon compound for etching semiconductor structures Dec 16, 2021 Issued
Array ( [id] => 17692117 [patent_doc_number] => 20220199410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => CONFORMAL AMORPHOUS CARBON LAYER ETCH WITH SIDE-WALL PASSIVATION [patent_app_type] => utility [patent_app_number] => 17/550182 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550182
CONFORMAL AMORPHOUS CARBON LAYER ETCH WITH SIDE-WALL PASSIVATION Dec 13, 2021 Abandoned
Array ( [id] => 18439922 [patent_doc_number] => 20230187217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH PATTERNS HAVING DIFFERENT HEIGHTS [patent_app_type] => utility [patent_app_number] => 17/550317 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550317 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550317
Method for preparing semiconductor device structure with patterns having different heights Dec 13, 2021 Issued
Array ( [id] => 18439923 [patent_doc_number] => 20230187218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH ISOLATION PATTERNS HAVING DIFFERENT HEIGHTS [patent_app_type] => utility [patent_app_number] => 17/550321 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550321
Method for preparing semiconductor device structure with isolation patterns having different heights Dec 13, 2021 Issued
Array ( [id] => 19071040 [patent_doc_number] => 20240105466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => METHOD FOR FORMING PATTERN OF METAL OXIDE AND METHOD FOR PRODUCING SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 18/273605 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18273605 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/273605
METHOD FOR FORMING PATTERN OF METAL OXIDE AND METHOD FOR PRODUCING SEMICONDUCTOR ELEMENT Dec 13, 2021 Pending
Array ( [id] => 18265946 [patent_doc_number] => 20230087188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => PLASMA ETCHING METHOD, PLASMA ETCHING APPARATUS, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/644154 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644154
PLASMA ETCHING METHOD, PLASMA ETCHING APPARATUS, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Dec 13, 2021 Abandoned
Array ( [id] => 19079442 [patent_doc_number] => 11948818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Temperature calibration with deposition and etch process [patent_app_type] => utility [patent_app_number] => 17/546769 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546769 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546769
Temperature calibration with deposition and etch process Dec 8, 2021 Issued
Array ( [id] => 18967411 [patent_doc_number] => 11901191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Atomic layer etching method and semiconductor device manufacturing method using the same [patent_app_type] => utility [patent_app_number] => 17/535933 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 10913 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535933
Atomic layer etching method and semiconductor device manufacturing method using the same Nov 25, 2021 Issued
Array ( [id] => 17963547 [patent_doc_number] => 20220344128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/532026 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532026
Substrate processing method and substrate processing apparatus Nov 21, 2021 Issued
Array ( [id] => 17963547 [patent_doc_number] => 20220344128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/532026 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532026
Substrate processing method and substrate processing apparatus Nov 21, 2021 Issued
Array ( [id] => 17963547 [patent_doc_number] => 20220344128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/532026 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532026
Substrate processing method and substrate processing apparatus Nov 21, 2021 Issued
Array ( [id] => 17963547 [patent_doc_number] => 20220344128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/532026 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532026
Substrate processing method and substrate processing apparatus Nov 21, 2021 Issued
Array ( [id] => 20566157 [patent_doc_number] => 12568784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Method of polishing carrier plate, carrier plate, and method of polishing semiconductor wafer [patent_app_type] => utility [patent_app_number] => 18/259100 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18259100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/259100
Method of polishing carrier plate, carrier plate, and method of polishing semiconductor wafer Nov 18, 2021 Issued
Array ( [id] => 18882813 [patent_doc_number] => 20240006182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD FOR ETCHING SILICON WAFER [patent_app_type] => utility [patent_app_number] => 18/252705 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18252705 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/252705
METHOD FOR ETCHING SILICON WAFER Nov 14, 2021 Pending
Array ( [id] => 17737964 [patent_doc_number] => 20220223426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE MANUFACTURING DEVICE [patent_app_type] => utility [patent_app_number] => 17/453850 [patent_app_country] => US [patent_app_date] => 2021-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453850 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453850
SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE MANUFACTURING DEVICE Nov 6, 2021 Abandoned
Array ( [id] => 19704891 [patent_doc_number] => 12198938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Etching method [patent_app_type] => utility [patent_app_number] => 17/517723 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7971 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517723 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517723
Etching method Nov 2, 2021 Issued
Array ( [id] => 17615335 [patent_doc_number] => 20220157615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => HIGH-THROUGHPUT DRY ETCHING OF FILMS CONTAINING SILICON-OXYGEN COMPONENTS OR SILICON-NITROGEN COMPONENTS BY PROTON-MEDIATED CATALYST FORMATION [patent_app_type] => utility [patent_app_number] => 17/515133 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/515133
High-throughput dry etching of films containing silicon-oxygen components or silicon-nitrogen components by proton-mediated catalyst formation Oct 28, 2021 Issued
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