Stephanie R. Berry

Array ( [id] => 11306682 [patent_doc_number] => 09514081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Asynchronous circuit with sequential write operations' [patent_app_type] => utility [patent_app_number] => 14/026371 [patent_app_country] => US [patent_app_date] => 2013-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 7860 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14026371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11180151 [patent_doc_number] => 09412145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'System and method for processing digital data' [patent_app_type] => utility [patent_app_number] => 14/013075 [patent_app_country] => US [patent_app_date] => 2013-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3355 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14013075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9200243 [patent_doc_number] => 20130339558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'Delegating Network Processor Operations to Star Topology Serial Bus Interfaces' [patent_app_type] => utility [patent_app_number] => 13/972797 [patent_app_country] => US [patent_app_date] => 2013-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 17516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13972797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10651250 [patent_doc_number] => 09367503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Electronic device with card interface' [patent_app_type] => utility [patent_app_number] => 13/948553 [patent_app_country] => US [patent_app_date] => 2013-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13948553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10969622 [patent_doc_number] => 20140372655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'System and Method for Symmetrical Direct Memory Access (SDMA)' [patent_app_type] => utility [patent_app_number] => 13/920095 [patent_app_country] => US [patent_app_date] => 2013-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2061 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13920095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11239118 [patent_doc_number] => 09465763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Bridge circuitry for communications with dynamically reconfigurable circuits' [patent_app_type] => utility [patent_app_number] => 13/919899 [patent_app_country] => US [patent_app_date] => 2013-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 9462 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13919899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10517825 [patent_doc_number] => 09244874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Selectively transparent bridge for peripheral component interconnect express bus systems' [patent_app_type] => utility [patent_app_number] => 13/918685 [patent_app_country] => US [patent_app_date] => 2013-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10230 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13918685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9200244 [patent_doc_number] => 20130339559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'METHOD TO CONTROL OPTICAL TRANSCEIVER IMPLEMENTED WITH A PLURALITY OF INNER SERIAL BUSES' [patent_app_type] => utility [patent_app_number] => 13/913680 [patent_app_country] => US [patent_app_date] => 2013-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4249 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13913680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11278829 [patent_doc_number] => 09495308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Offloading of computation for rack level servers and corresponding methods and systems' [patent_app_type] => utility [patent_app_number] => 13/900251 [patent_app_country] => US [patent_app_date] => 2013-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5180 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13900251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11200215 [patent_doc_number] => 09430429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Methods and apparatus to identify a communication protocol being used in a process control system' [patent_app_type] => utility [patent_app_number] => 13/888020 [patent_app_country] => US [patent_app_date] => 2013-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4081 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13888020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10194825 [patent_doc_number] => 09223736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Devices and methods for an enhanced driver mode for a shared bus' [patent_app_type] => utility [patent_app_number] => 13/886855 [patent_app_country] => US [patent_app_date] => 2013-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4191 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13886855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10922086 [patent_doc_number] => 20140325105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'MEMORY SYSTEM COMPONENTS FOR SPLIT CHANNEL ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/871437 [patent_app_country] => US [patent_app_date] => 2013-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5170 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13871437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10369193 [patent_doc_number] => 20150254198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'METHODS AND APPARATUS RELATED TO BUS ARBITRATION WITHIN A MULTI-MASTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/840390 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13840390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9745377 [patent_doc_number] => 20140281096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'BROADCASTING DEVICE WITH COMMUNICATION MECHANISM' [patent_app_type] => utility [patent_app_number] => 13/826073 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3165 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13826073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10194826 [patent_doc_number] => 09223737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-29 [patent_title] => 'Computer interconnect isolation' [patent_app_type] => utility [patent_app_number] => 13/826884 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13826884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11193403 [patent_doc_number] => 09424219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Direct routing between address spaces through a nontransparent peripheral component interconnect express bridge' [patent_app_type] => utility [patent_app_number] => 13/804839 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3959 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13804839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12332043 [patent_doc_number] => 09946675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Fault-tolerant loop for a communication bus [patent_app_type] => utility [patent_app_number] => 13/801936 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13801936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10562444 [patent_doc_number] => 09286121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Wireless bus for intra-chip and inter-chip communication, including data center/server embodiments' [patent_app_type] => utility [patent_app_number] => 13/793719 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 10360 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10046763 [patent_doc_number] => 09087162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Using a PCI standard hot plug controller to modify the hierarchy of a distributed switch' [patent_app_type] => utility [patent_app_number] => 13/777210 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 18664 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13777210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9644953 [patent_doc_number] => 20140223066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'Multi-Node Management Mechanism' [patent_app_type] => utility [patent_app_number] => 13/760311 [patent_app_country] => US [patent_app_date] => 2013-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13760311 [rel_patent_id] =>[rel_patent_doc_number] =>)