Search

Stephanie R. Berry

Examiner (ID: 47, Phone: (571)270-1662 , Office: P/3727 )

Most Active Art Unit
3727
Art Unit(s)
3723, 3727
Total Applications
481
Issued Applications
240
Pending Applications
2
Abandoned Applications
238

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10117710 [patent_doc_number] => 09152595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Processor-based system hybrid ring bus interconnects, and related devices, processor-based systems, and methods' [patent_app_type] => utility [patent_app_number] => 13/654653 [patent_app_country] => US [patent_app_date] => 2012-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9242 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13654653 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/654653
Processor-based system hybrid ring bus interconnects, and related devices, processor-based systems, and methods Oct 17, 2012 Issued
Array ( [id] => 9954280 [patent_doc_number] => 09003091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Flow control for a Serial Peripheral Interface bus' [patent_app_type] => utility [patent_app_number] => 13/655241 [patent_app_country] => US [patent_app_date] => 2012-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10172 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13655241 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/655241
Flow control for a Serial Peripheral Interface bus Oct 17, 2012 Issued
Array ( [id] => 8831590 [patent_doc_number] => 20130132635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'DIGITAL SIGNAL TRANSCEIVER SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/653987 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3755 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653987 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/653987
DIGITAL SIGNAL TRANSCEIVER SYSTEMS Oct 16, 2012 Abandoned
Array ( [id] => 9424040 [patent_doc_number] => 20140108691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'HANDLING INTERRUPTS IN A MULTI-PROCESSOR SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/653472 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653472 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/653472
Handling interrupts in a multi-processor system Oct 16, 2012 Issued
Array ( [id] => 9424039 [patent_doc_number] => 20140108690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'System And Method for Operating System Aware Low Latency Interrupt Handling' [patent_app_type] => utility [patent_app_number] => 13/649762 [patent_app_country] => US [patent_app_date] => 2012-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13649762 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/649762
System and method for operating system aware low latency interrupt handling Oct 10, 2012 Issued
Array ( [id] => 9398345 [patent_doc_number] => 20140095751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'FAST DESKEW WHEN EXITING LOW-POWER PARTIAL-WIDTH HIGH SPEED LINK STATE' [patent_app_type] => utility [patent_app_number] => 13/631876 [patent_app_country] => US [patent_app_date] => 2012-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4862 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13631876 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/631876
Fast deskew when exiting low-power partial-width high speed link state Sep 28, 2012 Issued
Array ( [id] => 9386063 [patent_doc_number] => 20140089546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'INTERRUPT TIMESTAMPING' [patent_app_type] => utility [patent_app_number] => 13/629509 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5341 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13629509 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/629509
Interrupt timestamping Sep 26, 2012 Issued
Array ( [id] => 9680393 [patent_doc_number] => 08819320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Executing an instruction for performing a configuration virtual topology change' [patent_app_type] => utility [patent_app_number] => 13/628413 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 19607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628413 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628413
Executing an instruction for performing a configuration virtual topology change Sep 26, 2012 Issued
Array ( [id] => 9967761 [patent_doc_number] => 09015396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Reducing latency in a peripheral component interconnect express link' [patent_app_type] => utility [patent_app_number] => 13/622266 [patent_app_country] => US [patent_app_date] => 2012-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13622266 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/622266
Reducing latency in a peripheral component interconnect express link Sep 17, 2012 Issued
Array ( [id] => 8735106 [patent_doc_number] => 20130080675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'Dual PCI-X/PCI-E Card' [patent_app_type] => utility [patent_app_number] => 13/618247 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13618247 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/618247
Dual PCI-X/PCI-E Card Sep 13, 2012 Abandoned
Array ( [id] => 8893617 [patent_doc_number] => 20130166801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'BUS BRIDGE APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/620294 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4970 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13620294 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/620294
BUS BRIDGE APPARATUS Sep 13, 2012 Abandoned
Array ( [id] => 9392264 [patent_doc_number] => 08688886 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-01 [patent_title] => 'Bus transaction maintenance protocol' [patent_app_type] => utility [patent_app_number] => 13/568639 [patent_app_country] => US [patent_app_date] => 2012-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8789 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13568639 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/568639
Bus transaction maintenance protocol Aug 6, 2012 Issued
Array ( [id] => 8497692 [patent_doc_number] => 20120297100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'STORAGE SYSTEM AND DATA TRANSMISSION METHOD' [patent_app_type] => utility [patent_app_number] => 13/564018 [patent_app_country] => US [patent_app_date] => 2012-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6663 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13564018 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/564018
STORAGE SYSTEM AND DATA TRANSMISSION METHOD Jul 31, 2012 Abandoned
Array ( [id] => 8893622 [patent_doc_number] => 20130166806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'PCI RISER CARD' [patent_app_type] => utility [patent_app_number] => 13/535439 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1128 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535439 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/535439
PCI RISER CARD Jun 27, 2012 Abandoned
Array ( [id] => 8661206 [patent_doc_number] => 20130042035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'Synchronization Of Data Between An Electronic Computing Mobile Device And An Electronic Computing Dockstation' [patent_app_type] => utility [patent_app_number] => 13/535650 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6912 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535650 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/535650
Synchronization of data between an electronic computing mobile device and an electronic computing dockstation Jun 27, 2012 Issued
Array ( [id] => 9207499 [patent_doc_number] => 20140006676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'SYSTEMS AND METHODS FOR DYNAMIC ALLOCATION OF INFORMATION HANDLING RESOURCES' [patent_app_type] => utility [patent_app_number] => 13/536023 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9087 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13536023 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/536023
SYSTEMS AND METHODS FOR DYNAMIC ALLOCATION OF INFORMATION HANDLING RESOURCES Jun 27, 2012 Abandoned
Array ( [id] => 9176293 [patent_doc_number] => 20130318278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'COMPUTING DEVICE AND METHOD FOR ADJUSTING BUS BANDWIDTH OF COMPUTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/535369 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1585 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535369 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/535369
COMPUTING DEVICE AND METHOD FOR ADJUSTING BUS BANDWIDTH OF COMPUTING DEVICE Jun 27, 2012 Abandoned
Array ( [id] => 9781351 [patent_doc_number] => 08856573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Setting a number (N) of fast training sequences (FTS) automatically to an optimal value' [patent_app_type] => utility [patent_app_number] => 13/534568 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5020 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13534568 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/534568
Setting a number (N) of fast training sequences (FTS) automatically to an optimal value Jun 26, 2012 Issued
Array ( [id] => 9207490 [patent_doc_number] => 20140006667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'ADAPTIVE HARDWARE INTERRUPT MODERATION' [patent_app_type] => utility [patent_app_number] => 13/534607 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13534607 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/534607
ADAPTIVE HARDWARE INTERRUPT MODERATION Jun 26, 2012 Abandoned
Array ( [id] => 9885856 [patent_doc_number] => 08972640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Controlling a physical link of a first protocol using an extended capability structure of a second protocol' [patent_app_type] => utility [patent_app_number] => 13/534541 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 18431 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13534541 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/534541
Controlling a physical link of a first protocol using an extended capability structure of a second protocol Jun 26, 2012 Issued
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