Search

Stephen C. Smith

Examiner (ID: 5832, Phone: (313)446-4914 , Office: P/2896 )

Most Active Art Unit
2896
Art Unit(s)
2895, 2896
Total Applications
248
Issued Applications
202
Pending Applications
0
Abandoned Applications
46

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13349801 [patent_doc_number] => 20180226440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => IMAGE SENSOR AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/942512 [patent_app_country] => US [patent_app_date] => 2018-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15942512 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/942512
Image sensor and method for forming the same Mar 30, 2018 Issued
Array ( [id] => 14151795 [patent_doc_number] => 10256287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Floating body contact circuit method for improving ESD performance and switching speed [patent_app_type] => utility [patent_app_number] => 15/910939 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 7785 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910939 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910939
Floating body contact circuit method for improving ESD performance and switching speed Mar 1, 2018 Issued
Array ( [id] => 12824455 [patent_doc_number] => 20180166657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/889659 [patent_app_country] => US [patent_app_date] => 2018-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/889659
Organic light emitting display apparatus and method of manufacturing the same Feb 5, 2018 Issued
Array ( [id] => 12849628 [patent_doc_number] => 20180175049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/886411 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15886411 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/886411
Semiconductor device and method of manufacturing the same Jan 31, 2018 Issued
Array ( [id] => 12873031 [patent_doc_number] => 20180182852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => HOMOEPITAXIAL TUNNEL BARRIERS WITH HYDROGENATED GRAPHENE-ON-GRAPHENE FOR ROOM TEMPERATURE ELECTRONIC DEVICE APPLICATIONS [patent_app_type] => utility [patent_app_number] => 15/883935 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15883935 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/883935
Homoepitaxial tunnel barriers with hydrogenated graphene-on-graphene for room temperature electronic device applications Jan 29, 2018 Issued
Array ( [id] => 13435283 [patent_doc_number] => 20180269184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => IMAGE DISPLAY MODULE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/868972 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868972 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/868972
Image display module and method of manufacturing the same, and display device Jan 10, 2018 Issued
Array ( [id] => 12801214 [patent_doc_number] => 20180158907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => NANOCRYSTALS WITH HIGH EXTINCTION COEFFICIENTS AND METHODS OF MAKING AND USING SUCH NANOCRYSTALS [patent_app_type] => utility [patent_app_number] => 15/867684 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15867684 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/867684
Nanocrystals with high extinction coefficients and methods of making and using such nanocrystals Jan 9, 2018 Issued
Array ( [id] => 12717190 [patent_doc_number] => 20180130896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => Semiconductor Strips with Undercuts and Methods for Forming the Same [patent_app_type] => utility [patent_app_number] => 15/864575 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15864575 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/864575
Semiconductor strips with undercuts and methods for forming the same Jan 7, 2018 Issued
Array ( [id] => 13755371 [patent_doc_number] => 10170640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => FinFET transistor gate and epitaxy formation [patent_app_type] => utility [patent_app_number] => 15/846520 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15846520 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/846520
FinFET transistor gate and epitaxy formation Dec 18, 2017 Issued
Array ( [id] => 13470871 [patent_doc_number] => 20180286978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => VERTICAL TRANSISTOR WITH BACK BIAS AND REDUCED PARASITIC CAPACITANCE [patent_app_type] => utility [patent_app_number] => 15/811830 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811830 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/811830
Vertical transistor with back bias and reduced parasitic capacitance Nov 13, 2017 Issued
Array ( [id] => 12236104 [patent_doc_number] => 20180068967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/795547 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6122 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795547 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/795547
Semiconductor device structure and manufacturing method Oct 26, 2017 Issued
Array ( [id] => 12223581 [patent_doc_number] => 20180061941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'STRUCTURE AND PROCESS TO TUCK FIN TIPS SELF-ALIGNED TO GATES' [patent_app_type] => utility [patent_app_number] => 15/794616 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8412 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794616 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/794616
Structure and process to tuck fin tips self-aligned to gates Oct 25, 2017 Issued
Array ( [id] => 13214951 [patent_doc_number] => 10121853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Structure and process to tuck fin tips self-aligned to gates [patent_app_type] => utility [patent_app_number] => 15/794636 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 8008 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794636 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/794636
Structure and process to tuck fin tips self-aligned to gates Oct 25, 2017 Issued
Array ( [id] => 14205663 [patent_doc_number] => 10269959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => High voltage transistor structure and method [patent_app_type] => utility [patent_app_number] => 15/728740 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 6363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728740 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728740
High voltage transistor structure and method Oct 9, 2017 Issued
Array ( [id] => 14094139 [patent_doc_number] => 10242983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Semiconductor device with increased source/drain area [patent_app_type] => utility [patent_app_number] => 15/723898 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 34 [patent_no_of_words] => 5748 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723898 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/723898
Semiconductor device with increased source/drain area Oct 2, 2017 Issued
Array ( [id] => 12117513 [patent_doc_number] => 20180001099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'Interconnect Structure and Method of Forming Same' [patent_app_type] => utility [patent_app_number] => 15/707399 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15707399 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/707399
Interconnect structure and method of forming same Sep 17, 2017 Issued
Array ( [id] => 13435495 [patent_doc_number] => 20180269290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => NITRIDE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/695659 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4947 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695659
Nitride semiconductor device Sep 4, 2017 Issued
Array ( [id] => 13030575 [patent_doc_number] => 10037911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Device layer transfer with a preserved handle wafer section [patent_app_type] => utility [patent_app_number] => 15/692666 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4088 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/692666
Device layer transfer with a preserved handle wafer section Aug 30, 2017 Issued
Array ( [id] => 13769799 [patent_doc_number] => 10177250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Method of manufacturing a semiconductor device with a metal-filled groove in a polysilicon gate electrode [patent_app_type] => utility [patent_app_number] => 15/679195 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 5945 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679195 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679195
Method of manufacturing a semiconductor device with a metal-filled groove in a polysilicon gate electrode Aug 16, 2017 Issued
Array ( [id] => 12990364 [patent_doc_number] => 20170345865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => SOLID-STATE IMAGING DEVICE [patent_app_type] => utility [patent_app_number] => 15/678790 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678790 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678790
Solid-state imaging device Aug 15, 2017 Issued
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