Stephen Chin

Array ( [id] => 3076376 [patent_doc_number] => 05295163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-15 [patent_title] => 'Synchronization method for a run length-limited (1,7)-code, and circuit arrangement for said method' [patent_app_type] => 1 [patent_app_number] => 7/929935 [patent_app_country] => US [patent_app_date] => 1992-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3303 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/295/05295163.pdf [firstpage_image] =>[orig_patent_app_number] => 929935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3490923 [patent_doc_number] => 05400365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Isk receiver' [patent_app_type] => 1 [patent_app_number] => 7/922616 [patent_app_country] => US [patent_app_date] => 1992-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3163 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/400/05400365.pdf [firstpage_image] =>[orig_patent_app_number] => 922616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3021660 [patent_doc_number] => 05276710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Carrier frequency error detector capable of accurately detecting a carrier frequency error' [patent_app_type] => 1 [patent_app_number] => 7/921711 [patent_app_country] => US [patent_app_date] => 1992-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7477 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276710.pdf [firstpage_image] =>[orig_patent_app_number] => 921711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3109605 [patent_doc_number] => 05319681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-07 [patent_title] => 'Method and a device for synchronizing a signal' [patent_app_type] => 1 [patent_app_number] => 7/922331 [patent_app_country] => US [patent_app_date] => 1992-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5107 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/319/05319681.pdf [firstpage_image] =>[orig_patent_app_number] => 922331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3002313 [patent_doc_number] => 05347540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Dynamic storage allocation in a logic analyzer' [patent_app_type] => 1 [patent_app_number] => 7/910059 [patent_app_country] => US [patent_app_date] => 1992-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6796 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/347/05347540.pdf [firstpage_image] =>[orig_patent_app_number] => 910059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3088040 [patent_doc_number] => 05297166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Method and apparatus for decision feedback equalization with reduced convergence time' [patent_app_type] => 1 [patent_app_number] => 7/907377 [patent_app_country] => US [patent_app_date] => 1992-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4440 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297166.pdf [firstpage_image] =>[orig_patent_app_number] => 907377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3030833 [patent_doc_number] => 05303263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Transmission channel characteristic equalizer' [patent_app_type] => 1 [patent_app_number] => 7/904337 [patent_app_country] => US [patent_app_date] => 1992-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 12477 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303263.pdf [firstpage_image] =>[orig_patent_app_number] => 904337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2980531 [patent_doc_number] => 05259007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-02 [patent_title] => 'Phase locked loop frequency synthesizer' [patent_app_type] => 1 [patent_app_number] => 7/899416 [patent_app_country] => US [patent_app_date] => 1992-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1873 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/259/05259007.pdf [firstpage_image] =>[orig_patent_app_number] => 899416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3033779 [patent_doc_number] => 05327465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Method and apparatus for squelch circuit in network communication' [patent_app_type] => 1 [patent_app_number] => 7/899083 [patent_app_country] => US [patent_app_date] => 1992-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 57 [patent_no_of_words] => 16269 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327465.pdf [firstpage_image] =>[orig_patent_app_number] => 899083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2961655 [patent_doc_number] => 05263049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Method and apparatus for CMOS differential drive having a rapid turn off' [patent_app_type] => 1 [patent_app_number] => 7/898871 [patent_app_country] => US [patent_app_date] => 1992-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 57 [patent_no_of_words] => 16322 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/263/05263049.pdf [firstpage_image] =>[orig_patent_app_number] => 898871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2988604 [patent_doc_number] => 05257293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Phase locked loop for extracting clock pulses through wave differential method' [patent_app_type] => 1 [patent_app_number] => 7/893446 [patent_app_country] => US [patent_app_date] => 1992-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4529 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/257/05257293.pdf [firstpage_image] =>[orig_patent_app_number] => 893446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2905502 [patent_doc_number] => 05272727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-21 [patent_title] => 'Adaptive maximum likelihood sequence estimator using channel estimators of respective order of impulse response' [patent_app_type] => 1 [patent_app_number] => 7/891641 [patent_app_country] => US [patent_app_date] => 1992-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2833 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/272/05272727.pdf [firstpage_image] =>[orig_patent_app_number] => 891641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2923489 [patent_doc_number] => 05228062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Method and apparatus for correcting for clock and carrier frequency offset, and phase jitter in multicarrier modems' [patent_app_type] => 1 [patent_app_number] => 7/889464 [patent_app_country] => US [patent_app_date] => 1992-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3923 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/228/05228062.pdf [firstpage_image] =>[orig_patent_app_number] => 889464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3088058 [patent_doc_number] => 05297167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Method and apparatus for detecting digital carrier signals on telephone cables' [patent_app_type] => 1 [patent_app_number] => 7/882687 [patent_app_country] => US [patent_app_date] => 1992-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2574 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297167.pdf [firstpage_image] =>[orig_patent_app_number] => 882687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2999484 [patent_doc_number] => 05267266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-30 [patent_title] => 'Fast converging adaptive equalizer using pilot adaptive filters' [patent_app_type] => 1 [patent_app_number] => 7/881046 [patent_app_country] => US [patent_app_date] => 1992-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3546 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/267/05267266.pdf [firstpage_image] =>[orig_patent_app_number] => 881046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3112824 [patent_doc_number] => 05315620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'Arrangement for correction of synchronous demodulator quadrature phase errors' [patent_app_type] => 1 [patent_app_number] => 7/877427 [patent_app_country] => US [patent_app_date] => 1992-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4584 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/315/05315620.pdf [firstpage_image] =>[orig_patent_app_number] => 877427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3040509 [patent_doc_number] => 05349613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Digital phase locked loop, and digital oscillator arranged to be used in the digital phase locked loop' [patent_app_type] => 1 [patent_app_number] => 7/876847 [patent_app_country] => US [patent_app_date] => 1992-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349613.pdf [firstpage_image] =>[orig_patent_app_number] => 876847 [rel_patent_id] =>[rel_patent_doc_number] =>)