Stephen D. Meier

Array ( [id] => 4123500 [patent_doc_number] => 06072219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Substrate-triggering electrostatic discharge protection circuit for deep-submicron integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/034529 [patent_app_country] => US [patent_app_date] => 1998-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6383 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072219.pdf [firstpage_image] =>[orig_patent_app_number] => 034529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4162686 [patent_doc_number] => 06157059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Nonvolatile floating gate memory with improved interpoly dielectric' [patent_app_type] => 1 [patent_app_number] => 9/036470 [patent_app_country] => US [patent_app_date] => 1998-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2471 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157059.pdf [firstpage_image] =>[orig_patent_app_number] => 036470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4242804 [patent_doc_number] => 06144084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Semiconductor integrated circuit having a logic verifying structure and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/031542 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 6185 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144084.pdf [firstpage_image] =>[orig_patent_app_number] => 031542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4161451 [patent_doc_number] => 06104061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Memory cell with vertical transistor and buried word and body lines' [patent_app_type] => 1 [patent_app_number] => 9/031620 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 8906 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104061.pdf [firstpage_image] =>[orig_patent_app_number] => 031620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363423 [patent_doc_number] => 06169301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Planar dielectric integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/030971 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6152 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169301.pdf [firstpage_image] =>[orig_patent_app_number] => 030971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4183807 [patent_doc_number] => 06037618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Intergrated field effect transistor device for high power and voltage amplification of RF signals' [patent_app_type] => 1 [patent_app_number] => 9/024821 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1886 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037618.pdf [firstpage_image] =>[orig_patent_app_number] => 024821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3943961 [patent_doc_number] => 05973348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/022391 [patent_app_country] => US [patent_app_date] => 1998-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 52 [patent_no_of_words] => 8850 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973348.pdf [firstpage_image] =>[orig_patent_app_number] => 022391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4091384 [patent_doc_number] => 06018169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Solid-state image sensor and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/019470 [patent_app_country] => US [patent_app_date] => 1998-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 11152 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018169.pdf [firstpage_image] =>[orig_patent_app_number] => 019470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4003031 [patent_doc_number] => 05986330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Enhanced planarization technique for an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/007668 [patent_app_country] => US [patent_app_date] => 1998-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2572 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986330.pdf [firstpage_image] =>[orig_patent_app_number] => 007668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4136913 [patent_doc_number] => 06034397 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Silicon-on-insulator body- and dual gate-coupled diode for electrostatic discharge (ESD) applications' [patent_app_type] => 1 [patent_app_number] => 9/002670 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 43 [patent_no_of_words] => 6715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034397.pdf [firstpage_image] =>[orig_patent_app_number] => 002670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3989854 [patent_doc_number] => 05959338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Micro electro-mechanical systems relay' [patent_app_type] => 1 [patent_app_number] => 8/999420 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1764 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959338.pdf [firstpage_image] =>[orig_patent_app_number] => 999420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3949630 [patent_doc_number] => 05990489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Thin film semiconductor apparatus and production method thereof' [patent_app_type] => 1 [patent_app_number] => 8/995880 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 64 [patent_no_of_words] => 10451 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990489.pdf [firstpage_image] =>[orig_patent_app_number] => 995880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197331 [patent_doc_number] => 06043526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Semiconductor memory cell using a ferroelectric thin film and a method for fabricating it' [patent_app_type] => 1 [patent_app_number] => 8/995841 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6244 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043526.pdf [firstpage_image] =>[orig_patent_app_number] => 995841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4140022 [patent_doc_number] => 06121678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Wrap-around interconnect for fine pitch ball grid array' [patent_app_type] => 1 [patent_app_number] => 8/994741 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3014 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121678.pdf [firstpage_image] =>[orig_patent_app_number] => 994741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4056081 [patent_doc_number] => 05969394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Method and structure for high aspect gate and short channel length insulated gate field effect transistors' [patent_app_type] => 1 [patent_app_number] => 8/993385 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3127 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969394.pdf [firstpage_image] =>[orig_patent_app_number] => 993385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3940391 [patent_doc_number] => 05929496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method and structure for channel length reduction in insulated gate field effect transistors' [patent_app_type] => 1 [patent_app_number] => 8/993767 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3064 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929496.pdf [firstpage_image] =>[orig_patent_app_number] => 993767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4108534 [patent_doc_number] => 06051870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Process for fabricating semiconductor device including improved phosphorous-doped silicon dioxide dielectric film' [patent_app_type] => 1 [patent_app_number] => 8/992333 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2572 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051870.pdf [firstpage_image] =>[orig_patent_app_number] => 992333 [rel_patent_id] =>[rel_patent_doc_number] =>)