Stephen D. Meier

Array ( [id] => 4009580 [patent_doc_number] => 06005280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Charge cancellation technique for integrated circuit resistors' [patent_app_type] => 1 [patent_app_number] => 8/989610 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3761 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005280.pdf [firstpage_image] =>[orig_patent_app_number] => 989610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892113 [patent_doc_number] => 05894150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Cell density improvement in planar DMOS with farther-spaced body regions and novel gates' [patent_app_type] => 1 [patent_app_number] => 8/986459 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 5152 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894150.pdf [firstpage_image] =>[orig_patent_app_number] => 986459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4187203 [patent_doc_number] => 06020623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Integrated structure with device having a preset reverse conduction threshold' [patent_app_type] => 1 [patent_app_number] => 8/984910 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2267 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020623.pdf [firstpage_image] =>[orig_patent_app_number] => 984910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4123399 [patent_doc_number] => 06072212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'EPROM cell array using N-tank as common source' [patent_app_type] => 1 [patent_app_number] => 8/978361 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3366 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072212.pdf [firstpage_image] =>[orig_patent_app_number] => 978361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4022079 [patent_doc_number] => 05907171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Method of making floating-gate memory-cell array with digital logic transistors' [patent_app_type] => 1 [patent_app_number] => 8/978363 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4571 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907171.pdf [firstpage_image] =>[orig_patent_app_number] => 978363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3952705 [patent_doc_number] => 05998822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Semiconductor integrated circuit and a method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/978429 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6422 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998822.pdf [firstpage_image] =>[orig_patent_app_number] => 978429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4095199 [patent_doc_number] => 06133640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Three-dimensional structure memory' [patent_app_type] => 1 [patent_app_number] => 8/971565 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7161 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133640.pdf [firstpage_image] =>[orig_patent_app_number] => 971565 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4049258 [patent_doc_number] => 05912493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Enhanced oxidation for spacer formation integrated with LDD implantation' [patent_app_type] => 1 [patent_app_number] => 8/970263 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5202 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912493.pdf [firstpage_image] =>[orig_patent_app_number] => 970263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3984864 [patent_doc_number] => 05949111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Semiconductor device and fabrication process therefor' [patent_app_type] => 1 [patent_app_number] => 8/966569 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 38 [patent_no_of_words] => 5670 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949111.pdf [firstpage_image] =>[orig_patent_app_number] => 966569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3980298 [patent_doc_number] => 05905276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Light emitting semiconductor device using nitrogen-Group III compound' [patent_app_type] => 1 [patent_app_number] => 8/968896 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3809 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905276.pdf [firstpage_image] =>[orig_patent_app_number] => 968896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3781775 [patent_doc_number] => 05818067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Thin film transistor and method for fabricating thereof' [patent_app_type] => 1 [patent_app_number] => 8/968863 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 3889 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818067.pdf [firstpage_image] =>[orig_patent_app_number] => 968863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3940175 [patent_doc_number] => 05929481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'High density trench DMOS transistor with trench bottom implant' [patent_app_type] => 1 [patent_app_number] => 8/964419 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3287 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929481.pdf [firstpage_image] =>[orig_patent_app_number] => 964419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3990357 [patent_doc_number] => 05910679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Method for fabricating semiconductor device having a crack resistant contact hole and a semiconductor device having a crack resistant hole' [patent_app_type] => 1 [patent_app_number] => 8/962269 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2179 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910679.pdf [firstpage_image] =>[orig_patent_app_number] => 962269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4080339 [patent_doc_number] => 05965925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Integrated circuit layout methods and layout structures' [patent_app_type] => 1 [patent_app_number] => 8/956203 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4729 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/965/05965925.pdf [firstpage_image] =>[orig_patent_app_number] => 956203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3746077 [patent_doc_number] => 05786627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Integrated circuit device and fabricating thereof' [patent_app_type] => 1 [patent_app_number] => 8/956497 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7577 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786627.pdf [firstpage_image] =>[orig_patent_app_number] => 956497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3961012 [patent_doc_number] => 05936279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method of fabricating self-align contact window with silicon nitride side wall' [patent_app_type] => 1 [patent_app_number] => 8/954410 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 3182 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936279.pdf [firstpage_image] =>[orig_patent_app_number] => 954410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3895861 [patent_doc_number] => 05834804 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Ferroelectric structure including MgTiO.sub.3 passivation' [patent_app_type] => 1 [patent_app_number] => 8/951433 [patent_app_country] => US [patent_app_date] => 1997-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3754 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834804.pdf [firstpage_image] =>[orig_patent_app_number] => 951433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3998229 [patent_doc_number] => 05892255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Ferroelectric based capacitor for use in memory systems and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/946749 [patent_app_country] => US [patent_app_date] => 1997-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3491 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892255.pdf [firstpage_image] =>[orig_patent_app_number] => 946749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892182 [patent_doc_number] => 05894155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Metal gate high voltage integrated circuit/process' [patent_app_type] => 1 [patent_app_number] => 8/947915 [patent_app_country] => US [patent_app_date] => 1997-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 4156 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894155.pdf [firstpage_image] =>[orig_patent_app_number] => 947915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4209585 [patent_doc_number] => 06078059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Fabrication of a thin film transistor and production of a liquid display apparatus' [patent_app_type] => 1 [patent_app_number] => 8/948141 [patent_app_country] => US [patent_app_date] => 1997-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6017 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078059.pdf [firstpage_image] =>[orig_patent_app_number] => 948141 [rel_patent_id] =>[rel_patent_doc_number] =>)