Search

Stephen D. Meier

Supervisory Patent Examiner (ID: 372, Phone: (571)272-2149 , Office: P/2853 )

Most Active Art Unit
2503
Art Unit(s)
2503, 2811, 2853, 2815, 2863, 2822
Total Applications
1320
Issued Applications
965
Pending Applications
40
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3668812 [patent_doc_number] => 05668396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Bipolar transistor having thin intrinsic base with low base resistance and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/533451 [patent_app_country] => US [patent_app_date] => 1995-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6139 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668396.pdf [firstpage_image] =>[orig_patent_app_number] => 533451 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/533451
Bipolar transistor having thin intrinsic base with low base resistance and method for fabricating the same Sep 24, 1995 Issued
Array ( [id] => 3557532 [patent_doc_number] => 05574301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Vertical switched-emitter structure with improved lateral isolation' [patent_app_type] => 1 [patent_app_number] => 8/528687 [patent_app_country] => US [patent_app_date] => 1995-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3020 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574301.pdf [firstpage_image] =>[orig_patent_app_number] => 528687 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/528687
Vertical switched-emitter structure with improved lateral isolation Sep 14, 1995 Issued
08/523003 INTEGRATED DUAL LAYER EMITTER MASK AND EMITTER TRENCH FOR BICMOS PROCESSES Aug 31, 1995 Abandoned
08/521461 SEMICONDUCTOR MEMORY DEVICE HAVING A FLOATING GATE Aug 29, 1995 Abandoned
Array ( [id] => 3664723 [patent_doc_number] => 05656822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Thin film transistor having increased effective channel width' [patent_app_type] => 1 [patent_app_number] => 8/520087 [patent_app_country] => US [patent_app_date] => 1995-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 984 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656822.pdf [firstpage_image] =>[orig_patent_app_number] => 520087 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/520087
Thin film transistor having increased effective channel width Aug 27, 1995 Issued
08/518703 SILICON DAMAGE FREE PROCESS FOR DOUBLE POLY EMITTER AND REVERSE MOS IN BICMOS APPLICATION Aug 23, 1995 Abandoned
Array ( [id] => 3781925 [patent_doc_number] => 05818078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Semiconductor device having a regrowth crystal region' [patent_app_type] => 1 [patent_app_number] => 8/517041 [patent_app_country] => US [patent_app_date] => 1995-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 13532 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818078.pdf [firstpage_image] =>[orig_patent_app_number] => 517041 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/517041
Semiconductor device having a regrowth crystal region Aug 20, 1995 Issued
Array ( [id] => 3729807 [patent_doc_number] => 05701019 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Semiconductor device having first and second stacked semiconductor layers, with electrical contact to the first semiconductor layer' [patent_app_type] => 1 [patent_app_number] => 8/517125 [patent_app_country] => US [patent_app_date] => 1995-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 6091 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701019.pdf [firstpage_image] =>[orig_patent_app_number] => 517125 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/517125
Semiconductor device having first and second stacked semiconductor layers, with electrical contact to the first semiconductor layer Aug 20, 1995 Issued
Array ( [id] => 3766401 [patent_doc_number] => 05844271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Single layer polycrystalline silicon split-gate EEPROM cell having a buried control gate' [patent_app_type] => 1 [patent_app_number] => 8/517495 [patent_app_country] => US [patent_app_date] => 1995-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 5762 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844271.pdf [firstpage_image] =>[orig_patent_app_number] => 517495 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/517495
Single layer polycrystalline silicon split-gate EEPROM cell having a buried control gate Aug 20, 1995 Issued
08/516905 VARIABLE CAPACITANCE SEMICONDUCTOR DIODE Aug 17, 1995 Abandoned
08/516961 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Aug 17, 1995 Abandoned
Array ( [id] => 3616400 [patent_doc_number] => 05565699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/509749 [patent_app_country] => US [patent_app_date] => 1995-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3433 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/565/05565699.pdf [firstpage_image] =>[orig_patent_app_number] => 509749 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/509749
Semiconductor integrated circuit device Aug 12, 1995 Issued
Array ( [id] => 3498585 [patent_doc_number] => 05508545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'Semiconductor device including a pair of transistors having a common channel region, and method of making the same' [patent_app_type] => 1 [patent_app_number] => 8/507685 [patent_app_country] => US [patent_app_date] => 1995-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2495 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/508/05508545.pdf [firstpage_image] =>[orig_patent_app_number] => 507685 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/507685
Semiconductor device including a pair of transistors having a common channel region, and method of making the same Jul 24, 1995 Issued
08/505787 BIMOS SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Jul 20, 1995 Abandoned
Array ( [id] => 3699786 [patent_doc_number] => 05596212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Semiconductor memory device and a manufacturing method of the same' [patent_app_type] => 1 [patent_app_number] => 8/505804 [patent_app_country] => US [patent_app_date] => 1995-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 35 [patent_no_of_words] => 9226 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596212.pdf [firstpage_image] =>[orig_patent_app_number] => 505804 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/505804
Semiconductor memory device and a manufacturing method of the same Jul 20, 1995 Issued
Array ( [id] => 3629753 [patent_doc_number] => 05621227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Method and apparatus for monolithic optoelectronic integrated circuit using selective epitaxy' [patent_app_type] => 1 [patent_app_number] => 8/503726 [patent_app_country] => US [patent_app_date] => 1995-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4248 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/621/05621227.pdf [firstpage_image] =>[orig_patent_app_number] => 503726 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/503726
Method and apparatus for monolithic optoelectronic integrated circuit using selective epitaxy Jul 17, 1995 Issued
08/500422 METHOD AND SYSTEM FOR PROTECTING A STACKED GATE EDGE IN A SEMICONDUCTOR DEVICE FROM SELF ALIGNED SOURCE (SAS) ETCH IN A SEMICONDUCTOR DEVICE Jul 10, 1995 Abandoned
Array ( [id] => 3626104 [patent_doc_number] => 05689126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Semiconductor memory device having stacked capacitor' [patent_app_type] => 1 [patent_app_number] => 8/499038 [patent_app_country] => US [patent_app_date] => 1995-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 2585 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689126.pdf [firstpage_image] =>[orig_patent_app_number] => 499038 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/499038
Semiconductor memory device having stacked capacitor Jul 5, 1995 Issued
08/498130 SCHOTTKY BARRIER INFRARED SENSOR Jul 4, 1995 Abandoned
Array ( [id] => 3652823 [patent_doc_number] => 05684320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Semiconductor device having transistor pair' [patent_app_type] => 1 [patent_app_number] => 8/497843 [patent_app_country] => US [patent_app_date] => 1995-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 67 [patent_no_of_words] => 22674 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684320.pdf [firstpage_image] =>[orig_patent_app_number] => 497843 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/497843
Semiconductor device having transistor pair Jul 2, 1995 Issued
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