Search

Stephen D. Rosasco

Examiner (ID: 7070, Phone: (571)272-1389 , Office: P/1721 )

Most Active Art Unit
1756
Art Unit(s)
1721, 1756, 1795, 1507, 1752, 1113, 1737
Total Applications
2769
Issued Applications
2461
Pending Applications
68
Abandoned Applications
246

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20234369 [patent_doc_number] => 20250291688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => ERROR RATE MEASUREMENT APPARATUS AND SIGNAL DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 19/024234 [patent_app_country] => US [patent_app_date] => 2025-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19024234 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/024234
ERROR RATE MEASUREMENT APPARATUS AND SIGNAL DETECTION METHOD Jan 15, 2025 Pending
Array ( [id] => 20009620 [patent_doc_number] => 20250147842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => MEMORY SYSTEM AND NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 19/013074 [patent_app_country] => US [patent_app_date] => 2025-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19013074 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/013074
MEMORY SYSTEM AND NONVOLATILE MEMORY Jan 7, 2025 Pending
Array ( [id] => 20103665 [patent_doc_number] => 20250233601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => ENCODING METADATA INFORMATION IN A CODEWORD [patent_app_type] => utility [patent_app_number] => 18/987205 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18987205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/987205
ENCODING METADATA INFORMATION IN A CODEWORD Dec 18, 2024 Pending
Array ( [id] => 19987601 [patent_doc_number] => 20250125823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => CONCATENATED POLAR CODE WITH ADAPTIVE ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 18/986548 [patent_app_country] => US [patent_app_date] => 2024-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18986548 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/986548
CONCATENATED POLAR CODE WITH ADAPTIVE ERROR DETECTION Dec 17, 2024 Pending
Array ( [id] => 19880478 [patent_doc_number] => 20250112735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => SHORT LATENCY FAST RETRANSMISSION TRIGGERING [patent_app_type] => utility [patent_app_number] => 18/979060 [patent_app_country] => US [patent_app_date] => 2024-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18979060 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/979060
SHORT LATENCY FAST RETRANSMISSION TRIGGERING Dec 11, 2024 Pending
Array ( [id] => 20428290 [patent_doc_number] => 20250390382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => ERROR CORRECTION CIRCUIT, STORAGE CONTROLLER INCLUDING ERROR CORRECTION CIRCUIT, AND STORAGE DEVICE INCLUDING STORAGE CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/977727 [patent_app_country] => US [patent_app_date] => 2024-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977727 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/977727
ERROR CORRECTION CIRCUIT, STORAGE CONTROLLER INCLUDING ERROR CORRECTION CIRCUIT, AND STORAGE DEVICE INCLUDING STORAGE CONTROLLER Dec 10, 2024 Pending
Array ( [id] => 20051356 [patent_doc_number] => 20250189578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => ERROR DETECTION SYSTEM APPLICABLE TO RTL MODULE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/960738 [patent_app_country] => US [patent_app_date] => 2024-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18960738 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/960738
ERROR DETECTION SYSTEM APPLICABLE TO RTL MODULE AND OPERATION METHOD THEREOF Nov 25, 2024 Pending
Array ( [id] => 20124291 [patent_doc_number] => 20250239322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => 3D STACK TESTING [patent_app_type] => utility [patent_app_number] => 18/951078 [patent_app_country] => US [patent_app_date] => 2024-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18951078 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/951078
3D STACK TESTING Nov 17, 2024 Pending
Array ( [id] => 19771385 [patent_doc_number] => 20250052811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES [patent_app_type] => utility [patent_app_number] => 18/929310 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18929310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/929310
INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES Oct 27, 2024 Issued
Array ( [id] => 19994641 [patent_doc_number] => 20250132863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => COMPUTING A POLAR TRANSFORMATION [patent_app_type] => utility [patent_app_number] => 18/917805 [patent_app_country] => US [patent_app_date] => 2024-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 986 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917805 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/917805
COMPUTING A POLAR TRANSFORMATION Oct 15, 2024 Pending
Array ( [id] => 19993749 [patent_doc_number] => 20250131971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => Method and device for correcting errors in resistive memories [patent_app_type] => utility [patent_app_number] => 18/917923 [patent_app_country] => US [patent_app_date] => 2024-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917923 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/917923
Method and device for correcting errors in resistive memories Oct 15, 2024 Pending
Array ( [id] => 20061684 [patent_doc_number] => 20250199906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => METHOD AND APPARATUS FOR FLEXIBLE ON-CHIP MEMORY CONFIGURATION TO SUPPORT MULTIPLE ERROR DETECTION AND CORRECTION MECHANISMS [patent_app_type] => utility [patent_app_number] => 18/893070 [patent_app_country] => US [patent_app_date] => 2024-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18893070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/893070
METHOD AND APPARATUS FOR FLEXIBLE ON-CHIP MEMORY CONFIGURATION TO SUPPORT MULTIPLE ERROR DETECTION AND CORRECTION MECHANISMS Sep 22, 2024 Pending
Array ( [id] => 20618012 [patent_doc_number] => 20260088115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => FASTER METHOD TO PREVENT HYBRID SINGLE LEVEL CELL DEFECTS IN SYSTEM [patent_app_type] => utility [patent_app_number] => 18/891932 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18891932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/891932
FASTER METHOD TO PREVENT HYBRID SINGLE LEVEL CELL DEFECTS IN SYSTEM Sep 19, 2024 Pending
Array ( [id] => 19851585 [patent_doc_number] => 20250096936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => COMMUNICATION SYSTEM, COMMUNICATION DEVICE AND COMMUNICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/882535 [patent_app_country] => US [patent_app_date] => 2024-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882535 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/882535
COMMUNICATION SYSTEM, COMMUNICATION DEVICE AND COMMUNICATION METHOD Sep 10, 2024 Pending
Array ( [id] => 19833560 [patent_doc_number] => 20250085346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => MERGED PARAMETRIC SCAN TOPOLOGY [patent_app_type] => utility [patent_app_number] => 18/828799 [patent_app_country] => US [patent_app_date] => 2024-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18828799 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/828799
MERGED PARAMETRIC SCAN TOPOLOGY Sep 8, 2024 Pending
Array ( [id] => 20569782 [patent_doc_number] => 20260063704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => REAL-TIME DEBUG IN LOW-POWER DEVICES [patent_app_type] => utility [patent_app_number] => 18/816685 [patent_app_country] => US [patent_app_date] => 2024-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18816685 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/816685
REAL-TIME DEBUG IN LOW-POWER DEVICES Aug 26, 2024 Issued
Array ( [id] => 19620079 [patent_doc_number] => 20240405759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => EMBEDDED PATTERN GENERATOR [patent_app_type] => utility [patent_app_number] => 18/805795 [patent_app_country] => US [patent_app_date] => 2024-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18805795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/805795
EMBEDDED PATTERN GENERATOR Aug 14, 2024 Pending
Array ( [id] => 20235533 [patent_doc_number] => 20250292852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => MEMORY DEVICE DETECTING FAIL OF THROUGH-SILICON VIA [patent_app_type] => utility [patent_app_number] => 18/798499 [patent_app_country] => US [patent_app_date] => 2024-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18798499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/798499
Memory device detecting fail of through-silicon via Aug 7, 2024 Issued
Array ( [id] => 19587687 [patent_doc_number] => 20240385244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => ADDRESSABLE TEST ACCESS PORT [patent_app_type] => utility [patent_app_number] => 18/786933 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/786933
ADDRESSABLE TEST ACCESS PORT Jul 28, 2024 Pending
Array ( [id] => 20331603 [patent_doc_number] => 12461880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Test data transfer in multi-die systems [patent_app_type] => utility [patent_app_number] => 18/785170 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2537 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785170 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/785170
Test data transfer in multi-die systems Jul 25, 2024 Issued
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