Stephen D. Rosasco

Array ( [id] => 19718868 [patent_doc_number] => 12204405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Storage device determining quickly whether error correction decoding has failed and method of operating the storage device [patent_app_type] => utility [patent_app_number] => 18/309806 [patent_app_country] => US [patent_app_date] => 2023-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8021 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19154317 [patent_doc_number] => 11979242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Transmission method, apparatus, and computer-readable storage medium [patent_app_type] => utility [patent_app_number] => 18/306563 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 20636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18556046 [patent_doc_number] => 20230254063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD [patent_app_type] => utility [patent_app_number] => 18/137716 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18137716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19899155 [patent_doc_number] => 12277076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Error correction for computational memory modules [patent_app_type] => utility [patent_app_number] => 18/302847 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 40 [patent_no_of_words] => 38695 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20167047 [patent_doc_number] => 20250259094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => QUANTUM ERROR CORRECTING CODES FROM HIGHER GRASSMANN CODES [patent_app_type] => utility [patent_app_number] => 18/857325 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18857325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18553297 [patent_doc_number] => 20230251309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES [patent_app_type] => utility [patent_app_number] => 18/135367 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18882644 [patent_doc_number] => 20240006013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => MEMORY DEVICE INCLUDING FLEXIBLE COLUMN REPAIR CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/296640 [patent_app_country] => US [patent_app_date] => 2023-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18296640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19481093 [patent_doc_number] => 20240329135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => TESTING MULTI-CYCLE PATHS USING SCAN TEST [patent_app_type] => utility [patent_app_number] => 18/193973 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18810039 [patent_doc_number] => 20230384374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => METHOD AND CIRCUIT FOR PERFORMING ERROR DETECTION ON A CLOCK GATED REGISTER SIGNAL [patent_app_type] => utility [patent_app_number] => 18/193446 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19485265 [patent_doc_number] => 20240333307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => ECC OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/128943 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18128943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18512604 [patent_doc_number] => 20230228814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/123406 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20137340 [patent_doc_number] => 20250244384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => TEMPLATIZED MEMORY PATTERN GENERATOR AND METHOD [patent_app_type] => utility [patent_app_number] => 18/688393 [patent_app_country] => US [patent_app_date] => 2023-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 533 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18688393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18834573 [patent_doc_number] => 20230403100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => GRAPH NEURAL NETWORK FOR CHANNEL DECODING [patent_app_type] => utility [patent_app_number] => 18/118637 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18118637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19175877 [patent_doc_number] => 20240161851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => TEST SYSTEMS CONFIGURED TO PERFORM TEST MODE OPERATIONS FOR MULTIPLE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/116019 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18116019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19442436 [patent_doc_number] => 12092691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Scan tree construction [patent_app_type] => utility [patent_app_number] => 18/115777 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4356 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 518 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18115777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19355151 [patent_doc_number] => 12055586 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-08-06 [patent_title] => 3D stacked die testing structure [patent_app_type] => utility [patent_app_number] => 18/113898 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18802425 [patent_doc_number] => 11835581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Interposer circuit [patent_app_type] => utility [patent_app_number] => 18/111682 [patent_app_country] => US [patent_app_date] => 2023-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 66 [patent_no_of_words] => 14324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18111682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18749505 [patent_doc_number] => 11808810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => AT-speed test access port operations [patent_app_type] => utility [patent_app_number] => 18/111679 [patent_app_country] => US [patent_app_date] => 2023-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 43 [patent_no_of_words] => 13148 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18111679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19458922 [patent_doc_number] => 12099411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Error processing circuit, memory and operation method of the memory [patent_app_type] => utility [patent_app_number] => 18/169880 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7103 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18883763 [patent_doc_number] => 20240007132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD, PROCESSING DEVICE AND STORAGE MEDIUM FOR CONSTRUCTING BASE MATRIX [patent_app_type] => utility [patent_app_number] => 18/169482 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169482 [rel_patent_id] =>[rel_patent_doc_number] =>)