Search

Stephen Gucker

Examiner (ID: 5682)

Most Active Art Unit
1649
Art Unit(s)
1646, 1812, 1818, 1649, 1645, 1647
Total Applications
799
Issued Applications
370
Pending Applications
114
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17809668 [patent_doc_number] => 20220261503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => COMPUTER-IMPLEMENTED METHOD FOR IMPROVING A SOCIAL NETWORK SITE COMUTER NETWORK, AND TERMINAL, SYSTEM AND COMPUTER READABLE MEDIUM FOR THE SAME [patent_app_type] => utility [patent_app_number] => 17/718312 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718312 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718312
COMPUTER-IMPLEMENTED METHOD FOR IMPROVING A SOCIAL NETWORK SITE COMUTER NETWORK, AND TERMINAL, SYSTEM AND COMPUTER READABLE MEDIUM FOR THE SAME Apr 10, 2022 Abandoned
Array ( [id] => 19029744 [patent_doc_number] => 11929107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Techniques for memory cell refresh [patent_app_type] => utility [patent_app_number] => 17/712972 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10041 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712972
Techniques for memory cell refresh Apr 3, 2022 Issued
Array ( [id] => 18983318 [patent_doc_number] => 11908503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Nonvolatile memory devices having enhanced write drivers therein [patent_app_type] => utility [patent_app_number] => 17/711297 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/711297
Nonvolatile memory devices having enhanced write drivers therein Mar 31, 2022 Issued
Array ( [id] => 17724427 [patent_doc_number] => 20220217149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => DYNAMIC AUTHORIZATION CONTROL SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/700322 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14885 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17700322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/700322
Dynamic authorization control system and method Mar 20, 2022 Issued
Array ( [id] => 17708766 [patent_doc_number] => 20220208774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MEMORY DEVICE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/698929 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/698929
Memory device and manufacturing method Mar 17, 2022 Issued
Array ( [id] => 18346692 [patent_doc_number] => 20230134802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => FERROELECTRIC MEMORY OPERATION BIAS AND POWER DOMAINS [patent_app_type] => utility [patent_app_number] => 17/696552 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696552 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/696552
Ferroelectric memory operation bias and power domains Mar 15, 2022 Issued
Array ( [id] => 19093689 [patent_doc_number] => 11955153 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-09 [patent_title] => Multi-element gain memory bit-cell having stacked and folded planar memory elements with and without offset [patent_app_type] => utility [patent_app_number] => 17/654908 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71120 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654908
Multi-element gain memory bit-cell having stacked and folded planar memory elements with and without offset Mar 14, 2022 Issued
Array ( [id] => 18651870 [patent_doc_number] => 20230297706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => DETECTION AND MITIGATION OF HIGH-RISK ONLINE ACTIVITY IN A COMPUTING PLATFORM [patent_app_type] => utility [patent_app_number] => 17/695715 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695715 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695715
Detection and mitigation of high-risk online activity in a computing platform Mar 14, 2022 Issued
Array ( [id] => 18617715 [patent_doc_number] => 20230284456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => ONE TRANSISTOR AND N MEMORY ELEMENT BASED MEMORY BIT-CELL HAVING STACKED AND FOLDED PLANAR MEMORY ELEMENTS WITH AND WITHOUT OFFSET [patent_app_type] => utility [patent_app_number] => 17/654905 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 71040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654905 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654905
One transistor and N memory element based memory bit-cell having stacked and folded planar memory elements with and without offset Mar 14, 2022 Issued
Array ( [id] => 19153838 [patent_doc_number] => 11978762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-07 [patent_title] => Planar capacitors with non-linear polar material staggered on a shared electrode [patent_app_type] => utility [patent_app_number] => 17/654802 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654802
Planar capacitors with non-linear polar material staggered on a shared electrode Mar 13, 2022 Issued
Array ( [id] => 19640478 [patent_doc_number] => 12171103 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-17 [patent_title] => Multi-input threshold gate having stacked and folded non-planar capacitors [patent_app_type] => utility [patent_app_number] => 17/654764 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71120 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654764 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654764
Multi-input threshold gate having stacked and folded non-planar capacitors Mar 13, 2022 Issued
Array ( [id] => 18985408 [patent_doc_number] => 11910618 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-20 [patent_title] => Multi-element ferroelectric gain memory bit-cell having stacked and folded non-planar capacitors [patent_app_type] => utility [patent_app_number] => 17/654562 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654562 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654562
Multi-element ferroelectric gain memory bit-cell having stacked and folded non-planar capacitors Mar 10, 2022 Issued
Array ( [id] => 18804105 [patent_doc_number] => 11837268 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-05 [patent_title] => Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset [patent_app_type] => utility [patent_app_number] => 17/654560 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71064 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654560 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654560
Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset Mar 10, 2022 Issued
Array ( [id] => 17691866 [patent_doc_number] => 20220199159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => PCRAM ANALOG PROGRAMMING BY A GRADUAL RESET COOLING STEP [patent_app_type] => utility [patent_app_number] => 17/692548 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692548 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/692548
PCRAM analog programming by a gradual reset cooling step Mar 10, 2022 Issued
Array ( [id] => 18969407 [patent_doc_number] => 11903219 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-13 [patent_title] => Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors [patent_app_type] => utility [patent_app_number] => 17/654526 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654526 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654526
Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors Mar 10, 2022 Issued
Array ( [id] => 19428296 [patent_doc_number] => 12087730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-09-10 [patent_title] => Multi-input threshold gate having stacked and folded planar capacitors with and without offset [patent_app_type] => utility [patent_app_number] => 17/654564 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71109 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654564
Multi-input threshold gate having stacked and folded planar capacitors with and without offset Mar 10, 2022 Issued
Array ( [id] => 19200589 [patent_doc_number] => 11997853 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-28 [patent_title] => 1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset [patent_app_type] => utility [patent_app_number] => 17/654379 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71127 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654379 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654379
1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset Mar 9, 2022 Issued
Array ( [id] => 19315949 [patent_doc_number] => 12041785 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-16 [patent_title] => 1TnC memory bit-cell having stacked and folded non-planar capacitors [patent_app_type] => utility [patent_app_number] => 17/654383 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654383 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654383
1TnC memory bit-cell having stacked and folded non-planar capacitors Mar 9, 2022 Issued
Array ( [id] => 19488866 [patent_doc_number] => 12108609 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-01 [patent_title] => Memory bit-cell with stacked and folded planar capacitors [patent_app_type] => utility [patent_app_number] => 17/653811 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 85 [patent_no_of_words] => 71076 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17653811 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/653811
Memory bit-cell with stacked and folded planar capacitors Mar 6, 2022 Issued
Array ( [id] => 18415817 [patent_doc_number] => 11670362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Sub-word line driver placement for memory device [patent_app_type] => utility [patent_app_number] => 17/687272 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17687272 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/687272
Sub-word line driver placement for memory device Mar 3, 2022 Issued
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