Search

Stephen J. Kalafut

Examiner (ID: 16306)

Most Active Art Unit
1745
Art Unit(s)
1111, 1795, 1754, 1745, 1741, 1727, 1107, 1102, 1104
Total Applications
3060
Issued Applications
2491
Pending Applications
181
Abandoned Applications
388

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20312547 [patent_doc_number] => 20250330176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => CLOCK TRANSMISSION CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/918069 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18918069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/918069
CLOCK TRANSMISSION CIRCUIT Oct 16, 2024 Pending
Array ( [id] => 19688961 [patent_doc_number] => 20250007506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => POWER SWITCH WITH NORMALLY ON TRANSISTOR [patent_app_type] => utility [patent_app_number] => 18/882850 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882850 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/882850
POWER SWITCH WITH NORMALLY ON TRANSISTOR Sep 11, 2024 Pending
Array ( [id] => 19851454 [patent_doc_number] => 20250096805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => CHARGE PUMP CIRCUIT AND PHASE-LOCKED LOOP CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/828011 [patent_app_country] => US [patent_app_date] => 2024-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18828011 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/828011
CHARGE PUMP CIRCUIT AND PHASE-LOCKED LOOP CIRCUIT Sep 8, 2024 Pending
Array ( [id] => 19635365 [patent_doc_number] => 20240413814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => OSCILLATING SIGNAL GENERATING CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/810138 [patent_app_country] => US [patent_app_date] => 2024-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18810138 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/810138
OSCILLATING SIGNAL GENERATING CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE SAME Aug 19, 2024 Pending
Array ( [id] => 20291888 [patent_doc_number] => 20250317131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => RECEIVER CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/805262 [patent_app_country] => US [patent_app_date] => 2024-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18805262 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/805262
RECEIVER CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME Aug 13, 2024 Pending
Array ( [id] => 20251772 [patent_doc_number] => 20250300641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => INPUT BUFFER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/776866 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776866
INPUT BUFFER CIRCUIT Jul 17, 2024 Pending
Array ( [id] => 19560761 [patent_doc_number] => 20240372553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => METHODS AND APPARATUS TO DYNAMICALLY CORRECT TIME KEEPING ERRORS [patent_app_type] => utility [patent_app_number] => 18/773777 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773777 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773777
METHODS AND APPARATUS TO DYNAMICALLY CORRECT TIME KEEPING ERRORS Jul 15, 2024 Pending
Array ( [id] => 19774020 [patent_doc_number] => 20250055446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => QUADRATURE PHASE SHIFTED CLOCK GENERATION WITH DUTY CYCLE CORRECTION [patent_app_type] => utility [patent_app_number] => 18/771327 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771327 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771327
QUADRATURE PHASE SHIFTED CLOCK GENERATION WITH DUTY CYCLE CORRECTION Jul 11, 2024 Pending
Array ( [id] => 20448954 [patent_doc_number] => 20260005680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => DIGITAL DUTY CYCLE CORRECTOR CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/756990 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756990 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756990
DIGITAL DUTY CYCLE CORRECTOR CIRCUIT Jun 26, 2024 Pending
Array ( [id] => 19867051 [patent_doc_number] => 20250105837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/739482 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739482 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739482
Semiconductor device Jun 10, 2024 Issued
Array ( [id] => 20389706 [patent_doc_number] => 12489444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Receiver circuit including differential buffer [patent_app_type] => utility [patent_app_number] => 18/739323 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739323 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739323
Receiver circuit including differential buffer Jun 10, 2024 Issued
Array ( [id] => 20410455 [patent_doc_number] => 20250379564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-11 [patent_title] => DEMODULATION CIRCUIT AND DIGITAL ISOLATOR [patent_app_type] => utility [patent_app_number] => 18/735140 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735140
DEMODULATION CIRCUIT AND DIGITAL ISOLATOR Jun 4, 2024 Pending
Array ( [id] => 20397759 [patent_doc_number] => 20250373234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => CROSS-COUPLED LATCH CHARGE PUMP AS WELL AS A METHOD OF OPERATING SUCH A CROSS-COUPLED LATCH CHARGE PUMP [patent_app_type] => utility [patent_app_number] => 18/679876 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679876 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679876
CROSS-COUPLED LATCH CHARGE PUMP AS WELL AS A METHOD OF OPERATING SUCH A CROSS-COUPLED LATCH CHARGE PUMP May 30, 2024 Pending
Array ( [id] => 20182866 [patent_doc_number] => 20250266824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => LOW POWER CONSUMPTION POWER-ON RESET SYSTEM [patent_app_type] => utility [patent_app_number] => 18/671940 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671940 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671940
LOW POWER CONSUMPTION POWER-ON RESET SYSTEM May 21, 2024 Pending
Array ( [id] => 20215874 [patent_doc_number] => 12412528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 18/668968 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6800 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668968
Display device May 19, 2024 Issued
Array ( [id] => 20089684 [patent_doc_number] => 20250219620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => STORAGE DEVICE HAVING LATCHING UNITS SERIALLY CONNECTED FOR IN-MEMORY ARITHMETIC OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/663560 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663560
STORAGE DEVICE HAVING LATCHING UNITS SERIALLY CONNECTED FOR IN-MEMORY ARITHMETIC OPERATIONS May 13, 2024 Pending
Array ( [id] => 19821891 [patent_doc_number] => 20250080098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => ON-RESISTANCE ENHANCEMENT FOR POWER CONVERTER [patent_app_type] => utility [patent_app_number] => 18/664044 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664044 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664044
ON-RESISTANCE ENHANCEMENT FOR POWER CONVERTER May 13, 2024 Pending
Array ( [id] => 19419775 [patent_doc_number] => 20240295898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => MULTI-CHIPLET CLOCK DELAY COMPENSATION [patent_app_type] => utility [patent_app_number] => 18/663864 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663864
MULTI-CHIPLET CLOCK DELAY COMPENSATION May 13, 2024 Pending
Array ( [id] => 19590722 [patent_doc_number] => 20240388279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => CLOCK OUTPUT DEVICE AND CLOCK DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 18/659520 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659520 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659520
CLOCK OUTPUT DEVICE AND CLOCK DETECTION METHOD May 8, 2024 Pending
Array ( [id] => 20469923 [patent_doc_number] => 12525966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Digital phase interpolator [patent_app_type] => utility [patent_app_number] => 18/636983 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636983 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636983
Digital phase interpolator Apr 15, 2024 Issued
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