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Stephen Kalinchak

Examiner (ID: 19315)

Most Active Art Unit
1103
Art Unit(s)
1103
Total Applications
234
Issued Applications
168
Pending Applications
1
Abandoned Applications
65

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18081278 [patent_doc_number] => 20220406890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => Semiconductor Structure, Method of Forming The Semiconductor Structure, and Semiconductor Device [patent_app_type] => utility [patent_app_number] => 17/845998 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845998 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/845998
Semiconductor Structure, Method of Forming The Semiconductor Structure, and Semiconductor Device Jun 20, 2022 Pending
Array ( [id] => 18081255 [patent_doc_number] => 20220406867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => DISPLAY PANEL AND ELECTRONIC DEVICE HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/841195 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841195
DISPLAY PANEL AND ELECTRONIC DEVICE HAVING THE SAME Jun 14, 2022 Pending
Array ( [id] => 20390675 [patent_doc_number] => 12490422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/841529 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 6378 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841529 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841529
Semiconductor memory device Jun 14, 2022 Issued
Array ( [id] => 18456520 [patent_doc_number] => 20230197802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => CONNECTION BETWEEN GATE AND SOURCE/DRAIN FEATURE [patent_app_type] => utility [patent_app_number] => 17/832597 [patent_app_country] => US [patent_app_date] => 2022-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832597 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/832597
CONNECTION BETWEEN GATE AND SOURCE/DRAIN FEATURE Jun 3, 2022 Pending
Array ( [id] => 18729469 [patent_doc_number] => 20230343765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => Dual Side Intelligent Power Device Integration [patent_app_type] => utility [patent_app_number] => 17/804928 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804928 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804928
Dual Side Intelligent Power Device Integration May 31, 2022 Pending
Array ( [id] => 18812914 [patent_doc_number] => 20230387251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/824690 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824690
GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE May 24, 2022 Pending
Array ( [id] => 18812914 [patent_doc_number] => 20230387251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/824690 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824690
GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE May 24, 2022 Pending
Array ( [id] => 18396749 [patent_doc_number] => 20230164970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => MEMORY DEVICES INCLUDING TRANSISTORS ON MULTIPLE LAYERS [patent_app_type] => utility [patent_app_number] => 17/743233 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743233 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743233
Memory devices including transistors on multiple layers May 11, 2022 Issued
Array ( [id] => 18396749 [patent_doc_number] => 20230164970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => MEMORY DEVICES INCLUDING TRANSISTORS ON MULTIPLE LAYERS [patent_app_type] => utility [patent_app_number] => 17/743233 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743233 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743233
Memory devices including transistors on multiple layers May 11, 2022 Issued
Array ( [id] => 18745721 [patent_doc_number] => 20230354718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => MAGNETIC TUNNEL JUNCTION STACK AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/734535 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734535
MAGNETIC TUNNEL JUNCTION STACK AND METHOD FOR MANUFACTURING THE SAME May 1, 2022 Pending
Array ( [id] => 18712977 [patent_doc_number] => 20230335610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/722381 [patent_app_country] => US [patent_app_date] => 2022-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9930 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722381 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722381
Semiconductor device structure and methods of forming the same Apr 16, 2022 Issued
Array ( [id] => 18680135 [patent_doc_number] => 20230317793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => STACKED FIELD EFFECT TRANSISTORS WITH REDUCED GATE-TO-DRAIN PARASITIC CAPACITANCE [patent_app_type] => utility [patent_app_number] => 17/709628 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709628 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/709628
STACKED FIELD EFFECT TRANSISTORS WITH REDUCED GATE-TO-DRAIN PARASITIC CAPACITANCE Mar 30, 2022 Pending
Array ( [id] => 18696585 [patent_doc_number] => 20230327026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => POWER SEMICONDUCTOR DEVICE WITH SHALLOW CONDUCTION REGION [patent_app_type] => utility [patent_app_number] => 17/705172 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705172
POWER SEMICONDUCTOR DEVICE WITH SHALLOW CONDUCTION REGION Mar 24, 2022 Pending
Array ( [id] => 20082581 [patent_doc_number] => 12356681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Semiconductor device and methods of manufacturing [patent_app_type] => utility [patent_app_number] => 17/654517 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 39 [patent_no_of_words] => 14353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654517 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654517
Semiconductor device and methods of manufacturing Mar 10, 2022 Issued
Array ( [id] => 18264480 [patent_doc_number] => 20230085722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/687130 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17687130 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/687130
SEMICONDUCTOR STORAGE DEVICE Mar 3, 2022 Abandoned
Array ( [id] => 18615961 [patent_doc_number] => 20230282700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => FIN ISOLATION STRUCTURES FORMED AFTER GATE METALLIZATION [patent_app_type] => utility [patent_app_number] => 17/685632 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685632
FIN ISOLATION STRUCTURES FORMED AFTER GATE METALLIZATION Mar 2, 2022 Pending
Array ( [id] => 17855465 [patent_doc_number] => 20220285508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/686093 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/686093
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Mar 2, 2022 Pending
Array ( [id] => 18615961 [patent_doc_number] => 20230282700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => FIN ISOLATION STRUCTURES FORMED AFTER GATE METALLIZATION [patent_app_type] => utility [patent_app_number] => 17/685632 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685632
FIN ISOLATION STRUCTURES FORMED AFTER GATE METALLIZATION Mar 2, 2022 Pending
Array ( [id] => 18600284 [patent_doc_number] => 20230275085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => GATE CUT GRID ACROSS INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/682037 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682037
GATE CUT GRID ACROSS INTEGRATED CIRCUIT Feb 27, 2022 Pending
Array ( [id] => 18600284 [patent_doc_number] => 20230275085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => GATE CUT GRID ACROSS INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/682037 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682037
GATE CUT GRID ACROSS INTEGRATED CIRCUIT Feb 27, 2022 Pending
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