Search

Stephen M. Baker

Examiner (ID: 15390)

Most Active Art Unit
2112
Art Unit(s)
2133, 2784, 2605, 2786, 2607, 2313, 2112, 2787, 2306
Total Applications
2021
Issued Applications
1703
Pending Applications
72
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7291205 [patent_doc_number] => 20040148556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Reduced complexity turbo decoding scheme' [patent_app_type] => new [patent_app_number] => 10/625485 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7084 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20040148556.pdf [firstpage_image] =>[orig_patent_app_number] => 10625485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/625485
Reduced complexity turbo decoding scheme Jul 22, 2003 Issued
Array ( [id] => 7474337 [patent_doc_number] => 20040054957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Memory-based shuffle-exchange traceback for gigabit ethernet transceiver' [patent_app_type] => new [patent_app_number] => 10/624774 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4193 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20040054957.pdf [firstpage_image] =>[orig_patent_app_number] => 10624774 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/624774
Memory-based shuffle-exchange traceback for gigabit Ethernet transceiver Jul 21, 2003 Issued
Array ( [id] => 7030880 [patent_doc_number] => 20050022100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Retraining derived clock receivers' [patent_app_type] => utility [patent_app_number] => 10/623605 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3165 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20050022100.pdf [firstpage_image] =>[orig_patent_app_number] => 10623605 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/623605
Retraining derived clock receivers Jul 21, 2003 Issued
Array ( [id] => 7271463 [patent_doc_number] => 20040059981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Method and encoder for implementing a fully protected multidimensional linear block code' [patent_app_type] => new [patent_app_number] => 10/622551 [patent_app_country] => US [patent_app_date] => 2003-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4139 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20040059981.pdf [firstpage_image] =>[orig_patent_app_number] => 10622551 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622551
Method and encoder for implementing a fully protected multidimensional linear block code Jul 20, 2003 Issued
Array ( [id] => 7675871 [patent_doc_number] => 20040153956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Apparatus and method for reducing bit error rates (BER) and frame error rates (FER) using turbo decoding in a digital communication system' [patent_app_type] => new [patent_app_number] => 10/622508 [patent_app_country] => US [patent_app_date] => 2003-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7188 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153956.pdf [firstpage_image] =>[orig_patent_app_number] => 10622508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622508
Apparatus and method for reducing Bit Error Rates (BER) and Frame Error Rates (FER) using turbo decoding in a digital communication system Jul 20, 2003 Issued
Array ( [id] => 7675892 [patent_doc_number] => 20040153935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Reduced overhead CRC functionality for packets and link layer superframes' [patent_app_type] => new [patent_app_number] => 10/623475 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3062 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153935.pdf [firstpage_image] =>[orig_patent_app_number] => 10623475 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/623475
Reduced overhead CRC functionality for packets and link layer superframes Jul 17, 2003 Abandoned
Array ( [id] => 953416 [patent_doc_number] => 06961888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'Methods and apparatus for encoding LDPC codes' [patent_app_type] => utility [patent_app_number] => 10/618325 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 9222 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/961/06961888.pdf [firstpage_image] =>[orig_patent_app_number] => 10618325 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618325
Methods and apparatus for encoding LDPC codes Jul 10, 2003 Issued
Array ( [id] => 7462282 [patent_doc_number] => 20040101274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Systems and methods for broadcasting information additive codes' [patent_app_type] => new [patent_app_number] => 10/618455 [patent_app_country] => US [patent_app_date] => 2003-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13671 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20040101274.pdf [firstpage_image] =>[orig_patent_app_number] => 10618455 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618455
Systems and methods for broadcasting information additive codes Jul 9, 2003 Issued
Array ( [id] => 691075 [patent_doc_number] => 07080309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Multiple ECC schemes to improve bandwidth' [patent_app_type] => utility [patent_app_number] => 10/615532 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3343 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080309.pdf [firstpage_image] =>[orig_patent_app_number] => 10615532 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/615532
Multiple ECC schemes to improve bandwidth Jul 6, 2003 Issued
Array ( [id] => 490552 [patent_doc_number] => 07222284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Low-density parity-check codes for multiple code rates' [patent_app_type] => utility [patent_app_number] => 10/608943 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 6234 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/222/07222284.pdf [firstpage_image] =>[orig_patent_app_number] => 10608943 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608943
Low-density parity-check codes for multiple code rates Jun 25, 2003 Issued
Array ( [id] => 992829 [patent_doc_number] => 06920603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Path error monitoring method and apparatus thereof' [patent_app_type] => utility [patent_app_number] => 10/609491 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9553 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/920/06920603.pdf [firstpage_image] =>[orig_patent_app_number] => 10609491 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/609491
Path error monitoring method and apparatus thereof Jun 24, 2003 Issued
Array ( [id] => 873795 [patent_doc_number] => 07366963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-29 [patent_title] => 'Data recording/reproduction device, data recording/reproduction method, and digital camera' [patent_app_type] => utility [patent_app_number] => 10/518061 [patent_app_country] => US [patent_app_date] => 2003-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6296 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/366/07366963.pdf [firstpage_image] =>[orig_patent_app_number] => 10518061 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/518061
Data recording/reproduction device, data recording/reproduction method, and digital camera Jun 18, 2003 Issued
Array ( [id] => 400689 [patent_doc_number] => 07296204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Error correction apparatus and method' [patent_app_type] => utility [patent_app_number] => 10/448710 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8797 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/296/07296204.pdf [firstpage_image] =>[orig_patent_app_number] => 10448710 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448710
Error correction apparatus and method May 29, 2003 Issued
Array ( [id] => 659562 [patent_doc_number] => 07111228 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-19 [patent_title] => 'System and method for performing parity checks in disk storage system' [patent_app_type] => utility [patent_app_number] => 10/429495 [patent_app_country] => US [patent_app_date] => 2003-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4235 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111228.pdf [firstpage_image] =>[orig_patent_app_number] => 10429495 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/429495
System and method for performing parity checks in disk storage system May 4, 2003 Issued
Array ( [id] => 823557 [patent_doc_number] => 07409627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-05 [patent_title] => 'Method for transmitting and receiving variable length packets based on forward error correction (FEC) coding' [patent_app_type] => utility [patent_app_number] => 10/428730 [patent_app_country] => US [patent_app_date] => 2003-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5667 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/409/07409627.pdf [firstpage_image] =>[orig_patent_app_number] => 10428730 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/428730
Method for transmitting and receiving variable length packets based on forward error correction (FEC) coding May 1, 2003 Issued
Array ( [id] => 609637 [patent_doc_number] => 07155656 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-26 [patent_title] => 'Method and system for decoding of binary shortened cyclic code' [patent_app_type] => utility [patent_app_number] => 10/427538 [patent_app_country] => US [patent_app_date] => 2003-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/155/07155656.pdf [firstpage_image] =>[orig_patent_app_number] => 10427538 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/427538
Method and system for decoding of binary shortened cyclic code Apr 30, 2003 Issued
Array ( [id] => 6703216 [patent_doc_number] => 20030226096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'True bit level decoding of TTCM (Turbo Trellis Code Modulation )' [patent_app_type] => new [patent_app_number] => 10/429362 [patent_app_country] => US [patent_app_date] => 2003-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 23171 [patent_no_of_claims] => 105 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20030226096.pdf [firstpage_image] =>[orig_patent_app_number] => 10429362 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/429362
True bit level decoding of TTCM (turbo trellis code modulation) of variable rates and signal constellations Apr 30, 2003 Issued
Array ( [id] => 7385512 [patent_doc_number] => 20040221220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Error detection and correction in a layered, 3-dimensional storage architecture' [patent_app_type] => new [patent_app_number] => 10/427525 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10614 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20040221220.pdf [firstpage_image] =>[orig_patent_app_number] => 10427525 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/427525
Error detection and correction in a layered, 3-dimensional storage architecture Apr 29, 2003 Issued
Array ( [id] => 7300672 [patent_doc_number] => 20040216026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Method and apparatus for interface failure survivability using error correction' [patent_app_type] => new [patent_app_number] => 10/425423 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20040216026.pdf [firstpage_image] =>[orig_patent_app_number] => 10425423 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425423
Method and apparatus for interface failure survivability using error correction Apr 27, 2003 Issued
Array ( [id] => 649137 [patent_doc_number] => 07120855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Survivor path memory circuit and Viterbi decoder with the same' [patent_app_type] => utility [patent_app_number] => 10/421768 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2917 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120855.pdf [firstpage_image] =>[orig_patent_app_number] => 10421768 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/421768
Survivor path memory circuit and Viterbi decoder with the same Apr 23, 2003 Issued
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