
Stephen M Baker
Examiner (ID: 13722)
| Most Active Art Unit | 2112 |
| Art Unit(s) | 2784, 2112, 2607, 2133, 2605, 2306, 2313, 2787, 2786 |
| Total Applications | 2021 |
| Issued Applications | 1703 |
| Pending Applications | 72 |
| Abandoned Applications | 247 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8194854
[patent_doc_number] => 08185810
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-05-22
[patent_title] => 'Low power viterbi trace back architecture'
[patent_app_type] => utility
[patent_app_number] => 11/787142
[patent_app_country] => US
[patent_app_date] => 2007-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1999
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/185/08185810.pdf
[firstpage_image] =>[orig_patent_app_number] => 11787142
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/787142 | Low power viterbi trace back architecture | Apr 12, 2007 | Issued |
Array
(
[id] => 8120247
[patent_doc_number] => 08161347
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-04-17
[patent_title] => 'Interleaving parity bits into user bits to guarantee run-length constraint'
[patent_app_type] => utility
[patent_app_number] => 11/787111
[patent_app_country] => US
[patent_app_date] => 2007-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2313
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/161/08161347.pdf
[firstpage_image] =>[orig_patent_app_number] => 11787111
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/787111 | Interleaving parity bits into user bits to guarantee run-length constraint | Apr 11, 2007 | Issued |
Array
(
[id] => 4602926
[patent_doc_number] => 07979771
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-12
[patent_title] => 'Erasure coding technique for scalable and fault tolerant storage system'
[patent_app_type] => utility
[patent_app_number] => 11/696654
[patent_app_country] => US
[patent_app_date] => 2007-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 20685
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/979/07979771.pdf
[firstpage_image] =>[orig_patent_app_number] => 11696654
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/696654 | Erasure coding technique for scalable and fault tolerant storage system | Apr 3, 2007 | Issued |
Array
(
[id] => 5012731
[patent_doc_number] => 20070283210
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-06
[patent_title] => 'Design of Spherical Lattice Codes for Lattice and Lattice-Reduction-Aided Decoders'
[patent_app_type] => utility
[patent_app_number] => 11/694241
[patent_app_country] => US
[patent_app_date] => 2007-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7325
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0283/20070283210.pdf
[firstpage_image] =>[orig_patent_app_number] => 11694241
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/694241 | Spherical lattice codes for lattice and lattice-reduction-aided decoders | Mar 29, 2007 | Issued |
Array
(
[id] => 4499213
[patent_doc_number] => 07886185
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-02-08
[patent_title] => 'Creation of a device database and synthesis of device driver information during dissimilar system restore'
[patent_app_type] => utility
[patent_app_number] => 11/690603
[patent_app_country] => US
[patent_app_date] => 2007-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 25247
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/886/07886185.pdf
[firstpage_image] =>[orig_patent_app_number] => 11690603
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/690603 | Creation of a device database and synthesis of device driver information during dissimilar system restore | Mar 22, 2007 | Issued |
Array
(
[id] => 4443591
[patent_doc_number] => 07900122
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-01
[patent_title] => 'Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation'
[patent_app_type] => utility
[patent_app_number] => 11/717469
[patent_app_country] => US
[patent_app_date] => 2007-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 9130
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/900/07900122.pdf
[firstpage_image] =>[orig_patent_app_number] => 11717469
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/717469 | Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation | Mar 12, 2007 | Issued |
Array
(
[id] => 5190532
[patent_doc_number] => 20070168841
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-19
[patent_title] => 'Frame format for millimeter-wave systems'
[patent_app_type] => utility
[patent_app_number] => 11/716968
[patent_app_country] => US
[patent_app_date] => 2007-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 11069
[patent_no_of_claims] => 89
[patent_no_of_ind_claims] => 21
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0168/20070168841.pdf
[firstpage_image] =>[orig_patent_app_number] => 11716968
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/716968 | Frame format for millimeter-wave systems | Mar 11, 2007 | Issued |
Array
(
[id] => 4700299
[patent_doc_number] => 20080222483
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-11
[patent_title] => 'Method, system, and apparatus for distributed decoding during prolonged refresh'
[patent_app_type] => utility
[patent_app_number] => 11/716199
[patent_app_country] => US
[patent_app_date] => 2007-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6134
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0222/20080222483.pdf
[firstpage_image] =>[orig_patent_app_number] => 11716199
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/716199 | Method, system, and apparatus for distributed decoding during prolonged refresh | Mar 7, 2007 | Issued |
Array
(
[id] => 4559813
[patent_doc_number] => 07877667
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-25
[patent_title] => 'Semiconductor memory'
[patent_app_type] => utility
[patent_app_number] => 11/714762
[patent_app_country] => US
[patent_app_date] => 2007-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6894
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/877/07877667.pdf
[firstpage_image] =>[orig_patent_app_number] => 11714762
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/714762 | Semiconductor memory | Mar 6, 2007 | Issued |
Array
(
[id] => 5221514
[patent_doc_number] => 20070162826
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-12
[patent_title] => 'Method for detecting error correction defects'
[patent_app_type] => utility
[patent_app_number] => 11/711531
[patent_app_country] => US
[patent_app_date] => 2007-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5890
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0162/20070162826.pdf
[firstpage_image] =>[orig_patent_app_number] => 11711531
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/711531 | Method for detecting error correction defects | Feb 26, 2007 | Abandoned |
Array
(
[id] => 28450
[patent_doc_number] => 07797613
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-09-14
[patent_title] => 'Digital implementation of an enhanced minsum algorithm for error correction in data communications'
[patent_app_type] => utility
[patent_app_number] => 11/678054
[patent_app_country] => US
[patent_app_date] => 2007-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2409
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/797/07797613.pdf
[firstpage_image] =>[orig_patent_app_number] => 11678054
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/678054 | Digital implementation of an enhanced minsum algorithm for error correction in data communications | Feb 21, 2007 | Issued |
Array
(
[id] => 8804968
[patent_doc_number] => 08443252
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-14
[patent_title] => 'Method and system of relaying data'
[patent_app_type] => utility
[patent_app_number] => 11/708631
[patent_app_country] => US
[patent_app_date] => 2007-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5090
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11708631
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/708631 | Method and system of relaying data | Feb 20, 2007 | Issued |
Array
(
[id] => 9012513
[patent_doc_number] => 08527834
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-03
[patent_title] => 'Information processing device and information processing method'
[patent_app_type] => utility
[patent_app_number] => 11/677216
[patent_app_country] => US
[patent_app_date] => 2007-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 6830
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11677216
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/677216 | Information processing device and information processing method | Feb 20, 2007 | Issued |
Array
(
[id] => 17536
[patent_doc_number] => 07805642
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-09-28
[patent_title] => 'Low power iterative decoder using input data pipelining and voltage scaling'
[patent_app_type] => utility
[patent_app_number] => 11/676946
[patent_app_country] => US
[patent_app_date] => 2007-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3305
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/805/07805642.pdf
[firstpage_image] =>[orig_patent_app_number] => 11676946
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/676946 | Low power iterative decoder using input data pipelining and voltage scaling | Feb 19, 2007 | Issued |
Array
(
[id] => 4874895
[patent_doc_number] => 20080201629
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-21
[patent_title] => 'METHOD AND SYSTEM FOR DETECTING SYNCHRONIZATION ERRORS IN PROGRAMS'
[patent_app_type] => utility
[patent_app_number] => 11/676853
[patent_app_country] => US
[patent_app_date] => 2007-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9520
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0201/20080201629.pdf
[firstpage_image] =>[orig_patent_app_number] => 11676853
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/676853 | Method and system for detecting synchronization errors in programs | Feb 19, 2007 | Issued |
Array
(
[id] => 5221511
[patent_doc_number] => 20070162823
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-12
[patent_title] => 'SYSTEM AND METHOD FOR OPTIMIZING ITERATIVE CIRCUIT FOR CYCLIC REDUNDENCY CHECK (CRC) CALCULATION'
[patent_app_type] => utility
[patent_app_number] => 11/676653
[patent_app_country] => US
[patent_app_date] => 2007-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5523
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0162/20070162823.pdf
[firstpage_image] =>[orig_patent_app_number] => 11676653
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/676653 | System and method for optimizing iterative circuit for cyclic redundency check (CRC) calculation | Feb 19, 2007 | Issued |
Array
(
[id] => 4449060
[patent_doc_number] => 07865812
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-04
[patent_title] => 'Apparatus and method for determining a detected punctured position in punctured convolutional codes'
[patent_app_type] => utility
[patent_app_number] => 11/675664
[patent_app_country] => US
[patent_app_date] => 2007-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6071
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/865/07865812.pdf
[firstpage_image] =>[orig_patent_app_number] => 11675664
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/675664 | Apparatus and method for determining a detected punctured position in punctured convolutional codes | Feb 15, 2007 | Issued |
Array
(
[id] => 796948
[patent_doc_number] => 07430706
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-09-30
[patent_title] => 'Diagonal interleaved parity calculator'
[patent_app_type] => utility
[patent_app_number] => 11/676071
[patent_app_country] => US
[patent_app_date] => 2007-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4717
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/430/07430706.pdf
[firstpage_image] =>[orig_patent_app_number] => 11676071
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/676071 | Diagonal interleaved parity calculator | Feb 15, 2007 | Issued |
Array
(
[id] => 4462654
[patent_doc_number] => 07895507
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-02-22
[patent_title] => 'Add-compare-select structures using 6-input lookup table architectures'
[patent_app_type] => utility
[patent_app_number] => 11/707311
[patent_app_country] => US
[patent_app_date] => 2007-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 5427
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/895/07895507.pdf
[firstpage_image] =>[orig_patent_app_number] => 11707311
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/707311 | Add-compare-select structures using 6-input lookup table architectures | Feb 15, 2007 | Issued |
Array
(
[id] => 5047619
[patent_doc_number] => 20070266293
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-15
[patent_title] => 'Apparatus and method for high speed data transceiving, and apparatus and method for error-correction processing for the same'
[patent_app_type] => utility
[patent_app_number] => 11/707029
[patent_app_country] => US
[patent_app_date] => 2007-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 6974
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0266/20070266293.pdf
[firstpage_image] =>[orig_patent_app_number] => 11707029
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/707029 | Apparatus and method for high speed data transceiving, and apparatus and method for error-correction processing for the same | Feb 15, 2007 | Abandoned |