Search

Stephen Michael Gravini

Examiner (ID: 12967, Phone: (571)272-4875 , Office: P/3744 )

Most Active Art Unit
3753
Art Unit(s)
3749, 3753, 2162, 3743, 3404, 3744, 3622
Total Applications
3725
Issued Applications
2988
Pending Applications
212
Abandoned Applications
561

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18303279 [patent_doc_number] => 11625180 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-11 [patent_title] => Fault tolerant reservation state distribution for multi-partition logical volumes [patent_app_type] => utility [patent_app_number] => 17/118300 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118300 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/118300
Fault tolerant reservation state distribution for multi-partition logical volumes Dec 9, 2020 Issued
Array ( [id] => 18015021 [patent_doc_number] => 11507317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Establishing a delay period associated with a program resume operation of a memory subsystem [patent_app_type] => utility [patent_app_number] => 17/100334 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100334 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/100334
Establishing a delay period associated with a program resume operation of a memory subsystem Nov 19, 2020 Issued
Array ( [id] => 16713972 [patent_doc_number] => 20210081119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => CONFIGURABLE HYPERCONVERGED MULTI-TENANT STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/096613 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096613 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096613
Configurable hyperconverged multi-tenant storage system Nov 11, 2020 Issued
Array ( [id] => 16623393 [patent_doc_number] => 20210042046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => MEMORY SYSTEMS HAVING SEMICONDUCTOR MEMORY MODULES THEREIN THAT SUPPORT PAGE FAULT PROCESSING [patent_app_type] => utility [patent_app_number] => 17/082448 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082448 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/082448
Memory systems having semiconductor memory modules therein that support page fault processing Oct 27, 2020 Issued
Array ( [id] => 17715377 [patent_doc_number] => 11379368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-05 [patent_title] => External way allocation circuitry for processor cores [patent_app_type] => utility [patent_app_number] => 17/081151 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9134 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081151 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081151
External way allocation circuitry for processor cores Oct 26, 2020 Issued
Array ( [id] => 17084164 [patent_doc_number] => 20210279170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => Data storage device and data processing method [patent_app_type] => utility [patent_app_number] => 17/080856 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080856 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/080856
Data storage device and data processing method Oct 26, 2020 Issued
Array ( [id] => 17667202 [patent_doc_number] => 11360901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Method and apparatus for managing page cache for multiple foreground applications [patent_app_type] => utility [patent_app_number] => 17/073493 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6309 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/073493
Method and apparatus for managing page cache for multiple foreground applications Oct 18, 2020 Issued
Array ( [id] => 17861696 [patent_doc_number] => 11442854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Balancing memory-portion accesses [patent_app_type] => utility [patent_app_number] => 17/070774 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11339 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070774 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/070774
Balancing memory-portion accesses Oct 13, 2020 Issued
Array ( [id] => 16764239 [patent_doc_number] => 20210109820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => BACKUP AND RESTORE OF LINKED CLONE VM [patent_app_type] => utility [patent_app_number] => 17/069604 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069604 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069604
Backup and restore of linked clone VM Oct 12, 2020 Issued
Array ( [id] => 19092595 [patent_doc_number] => 11954044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Translation lookaside buffer prewarming [patent_app_type] => utility [patent_app_number] => 17/068713 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068713 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068713
Translation lookaside buffer prewarming Oct 11, 2020 Issued
Array ( [id] => 18855647 [patent_doc_number] => 11853225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Software-hardware memory management modes [patent_app_type] => utility [patent_app_number] => 17/068730 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068730
Software-hardware memory management modes Oct 11, 2020 Issued
Array ( [id] => 17522045 [patent_doc_number] => 20220107894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => APPARATUS AND METHOD FOR CONTROLLING EVICTION FROM A STORAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/064019 [patent_app_country] => US [patent_app_date] => 2020-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17064019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/064019
Apparatus and method for controlling eviction from a storage structure Oct 5, 2020 Issued
Array ( [id] => 17409028 [patent_doc_number] => 11249913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Continuous read with multiple read commands [patent_app_type] => utility [patent_app_number] => 17/061451 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 10855 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17061451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/061451
Continuous read with multiple read commands Sep 30, 2020 Issued
Array ( [id] => 17415880 [patent_doc_number] => 20220050784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => METHOD AND SYSTEM FOR LOGICAL TO PHYSICAL (L2P) MAPPING FOR DATA-STORAGE DEVICE COMPRISING NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/039268 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039268 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/039268
Method and system for logical to physical (L2P) mapping for data-storage device comprising nonvolatile memory Sep 29, 2020 Issued
Array ( [id] => 16584863 [patent_doc_number] => 20210019265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => METHOD AND SYSTEM OF REDUCING FTL ADDRESS MAPPING SPACE [patent_app_type] => utility [patent_app_number] => 17/037156 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037156 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037156
Method and system of reducing address mapping space of flash translation layer Sep 28, 2020 Issued
Array ( [id] => 17128407 [patent_doc_number] => 20210303176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => CONTROLLER, OPERATING METHOD OF THE CONTROLLER AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/036759 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036759
Controller, operating method of the controller and memory system Sep 28, 2020 Issued
Array ( [id] => 17977440 [patent_doc_number] => 11494300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Page table walker with page table entry (PTE) physical address prediction [patent_app_type] => utility [patent_app_number] => 17/033737 [patent_app_country] => US [patent_app_date] => 2020-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033737
Page table walker with page table entry (PTE) physical address prediction Sep 25, 2020 Issued
Array ( [id] => 19522997 [patent_doc_number] => 12124724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Memory migration method, apparatus, and computing device [patent_app_type] => utility [patent_app_number] => 17/761536 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 14624 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17761536 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/761536
Memory migration method, apparatus, and computing device Sep 22, 2020 Issued
Array ( [id] => 17484471 [patent_doc_number] => 20220091975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => MEMORY SUB-SYSTEM LOGICAL BLOCK ADDRESS REMAPPING [patent_app_type] => utility [patent_app_number] => 17/027895 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027895 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027895
Memory sub-system logical block address remapping Sep 21, 2020 Issued
Array ( [id] => 17423175 [patent_doc_number] => 11256629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Cache filtering [patent_app_type] => utility [patent_app_number] => 17/027271 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027271 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027271
Cache filtering Sep 20, 2020 Issued
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